Design for testability arm established

To attain desired yield levels, it has become imperative to invest additional time and effort in developing custom DFT strategies. TVS’s asureDFT services suite addresses this need by helping clients design and implement a DFT strategy that delivers improved execution, quality and reduced time-to market.

“asureDFT is a natural extension of TVS’s core expertise in the hardware verification domain,” said Mike Bartley, TVS founder and CEO. “TVS can deliver end-to-end DFT support - from design all the way up to silicon. For organizations looking to develop a DFT methodology, TVS can help reduce project overheads by eliminating the need to hire costly DFT resources. For organizations that already have a DFT architecture in place, TVS can provide an assessment and suggest improvements to the existing methodology.”

The TVS asureDFT services suite includes Scan, ATPG, Memory BIST (MBIST), Logic BIST (LBIST), JTAG, Formal Verification and ATE support. These are augmented by training support for DFT strategy/structural testing, together with exclusive training for JTAG, Scan, Boundary Scan and MBIST. TVS can also provide off-the-shelf components for JTAG TAP based test controllers, test suites for verifying BSCAN, generate tester compatible vectors for ATE and format conversions with ATE logs for diagnosis.

“asureDFT is a one-stop shop for a wide range of DFT solutions encompassing services, training, off-the-shelf components and DFT methodology development and assessment”, concluded Mike Bartley, TVS founder and CEO.