Test & Measurement

New Boundary Scan fixture allows structural testing of PCI Express Plug-In Cards via IEEE1149.6

21st October 2008
ES Admin
0
GOEPEL electronic, leading manufacturer of JTAG / Boundary Scan solutions compliant with IEEE1149.x, announced the launch of a new interface test fixture, CION Fixture™ /PCIe-x16, a further addition to the popular CION Fixture™ family. The new low cost fixture provides a predefined PCI Express x16 Slot, in which the card to be tested is inserted and thereby connected to a TAP (Test Access Port). Due to the integrated test channels IEEE 1149.1 and IEEE1149.6 virtually all PCI Express High Speed and Low Speed signal pins can be structurally tested if there are compatible interfaces.
“Nearly all providers of PCI Express interface circuits support the IEEE1149.6 standard in their latest generation of products, these can be structurally tested by our new fixture at prototype and pre-production” says Karl Miles, UK Sales Manager of GOEPEL electronics. “At the same time we strengthen our market-leading position with a broad product range for the structural interface test via IEEE1149.1 and IEEE1149.6.”

The CION Fixture™ / PCIe-x16 can be used for every kind of PCI Express Interface x1, x4, x8, x12, x16 and is compatible with the PCI Express Standard Version 2.0. The signal pins are tested using a dot1 / dot6 interconnection test with a CION Module™ / PCIe x(X) that can be inserted in the fixture as well.

The new hardware modules are supported by all Boundary Scan controllers of the ScanBooster™ or SCANFLEX® family, as well as by the integrated software platform SYSTEM CASCON™. The latter is the most ground-breaking integrated JTAG / Boundary Scan development environment within the professional domain for over 10 years and brings along 38 fully integrated tools. Through this the operator can easily apply the CION Fixture™ /PCIe-x16 to an appropriate pilot project and generate the required dot1 / dot6 test vectors fully automatic (ATPG). Furthermore, he can debug interactively and visualise possible failures in the pin and net mode.

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