Lauterbach Leads The Way with High Speed Serial Trace Debug Technology

The trace interface, over which the processors deliver the detailed information on the operation of their inner processes, has struggled to keep up with the growing flood of information as processors have become more complex and faster, said Barry Lock, Manager of Lauterbach UK. For many developers of embedded systems it would be unthinkable to undertake a development without this important information, so a lot of effort has been made to increase the data throughput of the trace interface.



For many years the increase in clock frequency and a greater bus-width at the trace port were an effective way of increasing data volumes. However, these measures have their price. Not only does a wider trace port take up highly coveted package pins, but also, poor signal quality at higher clock frequencies requires compensation on all signals from the trace bus.



In recent times, ARM has implemented this technology with its High Speed Serial Trace Port (HSSTP). This was quickly followed by AMCC with the Titan, Freescale with the QorIQ processors P4040 and P4080 and Marvell with the SETM3.



At Lauterbach we have taken the lead in the design of the hardware interface for serial trace, said Barry Lock. A universal preprocessor was developed on the basis of the Aurora protocol. Only the firmware and software have to be changed to record any of the alternative protocols. This means that our system is already prepared for further variants of serial trace protocols. This will be exciting news for engineers working at the leading edge of microprocessor based systems.



The “Preprocessor HSSTP” is designed for a maximum of four high-speed channels. The following transmission rates are supported:

6.25 GBit/s per channel with up to 3 channels

3.125 GBit/s per channel with 4 channels



The trace data is provided via a custom connector system from Samtec (ERF8, 40 pins). For transmission, ARM-HSSTP uses the Xilinx Aurora Protocol. The parallel trace data is 8b / 10b coded and serialized on the ARM core. Differential GBit transceivers send the data flow by cable to the “Preprocessor

HSSTP” from Lauterbach, which recovers the original parallel trace data from the serial transmission.



The large volume of trace data obviously requires a correspondingly large trace memory. This is available from the Lauterbach's 'PowerTrace II' with a memory extension of up to 4 GBytes.