A BGA (ball grid array) interposer solution for testing DDR4 x16 DRAM (dynamic random access memory) designs with a logic analyser has been introduced by Keysight Technologies. Using the W4636A DDR4 x 16 BGA interposer solution, engineers can quickly and accurately capture address and command signals, and a subset of data signals, for debugging designs and performing functional validation measurements for data rates up to 2,400Mb/s.
It is suitable for testing designs with tight space restrictions. As the memory industry transitions to DDR4 designs, engineers working on next-gen memory systems - such as those used in servers and embedded devices - face significant challenges. Probing and accurate signal capture are becoming increasingly critical for debug and validation of designs.
This two-wing, small-KOV (keep-out volume), BGA interposer is for engineers who need to view DDR4 x16 DRAM traffic and have limited KOV on their systems under test. It is also for engineers who need to perform functional compliance tests on DDR4 devices with ADD/CMD signals.
The interposer solution provides direct access to the balls of JEDEC-standard DDR4 x16 96-ball DRAM with low loading and minimal impact to signal integrity on embedded-system designs. The interposer solution is designed to be used with the U4154B logic analysis system, E5847A ZIF (zero insertion force) probes and U4201A cables for functional compliance and performance validation and analysis on ADD/CMD and a subset of DQ (data).
For engineers who require access to all ADD/CMD/DQ/DQS at data rates more than 2,400Mb/s, the W4633A x4/x8 DDR4 BGA interposer and W4631A x16 DDR4 BGA interposers capture all ADD/CMD/DQ/DQS signals at data rates of at least 3.2Gb/s.
The U4154B logic analysis module with 4Gb/s state speed enables engineers to reliably trigger on specific events and capture DDR4 traffic. When used with the new DDR4 interposer solutions, B4621B DDR decoder and B4622B compliance software toolset, this module provides functional test capability for system integration in the memory industry with visibility of the upper data byte lane up to 2,400Mb/s.