SSIC/CSI-3 support enhances protocol analyser

SSIC (SuperSpeed USB Inter-Chip) allows USB-enabled functionality to work in M-PHY-based mobile systems.

Mobile designers are adding multiple high-speed buses to their designs to manage multiple high-resolution cameras, advanced graphics adapters and on-board memory. These high-speed buses contribute to increasing demand for bandwidth, which has driven the expansion of the M-PHY specification to include four-lane, 6.0Gbs options. The U4431A offers up to 16GB of analysis memory on each lane, allowing designers to capture tens of seconds of system traffic, even at these high speeds.

In addition, the analyser offers a raw data mode, a feature that lets designers see the time-correlated 8b/10b data that underlies each protocol. Designers can view the data in a waveform or listing format, providing insight into how a packet is formed at the physical layer.

The visibility extends throughout the M-PHY protocol stack, allowing error detection from the physical layer to the link and from the transport layers to the high-level application layer. These views allow engineers to unravel data as it travels throughout the entire transmission process.

The analyser also offers powerful tools to help designers isolate and unravel specific events on the bus. Real-time triggers allow designers to detect errors at each layer of the protocol; filters focus analytic tools on specific types of traffic; and traffic overviews and measurement markers help designers understand traffic from entire bursts to nanosecond-resolution detail.

The modular AXIe blade form of the analyser allows users to analyse multiple M-PHY buses simultaneously. These M-PHY buses can be time-correlated with MIPI D-PHY CSI-2 and DSI-1, PCIe, DDR and HDMI buses—or even generic high-speed logic analyser modules. Designers can purchase as many lanes and as much memory and protocol support as they need today, and upgrade in the future.

Agilent also announced preliminary support for Mobile PCI Express (M-PCIe). Early adopters are testing the initial Agilent firmware release, with availability to all customers to be announced in the second quarter of 2014. M-PCIe maps the broadly adopted PCIe standard to the M-PHY physical layer, and it will be first seen in memory applications.