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Access IS has today announced the introduction of the LSR116 - a compact sealed, water and dust-resistant 2D barcode reader which produces exceptionally fast and accurate reading of barcode data from smartphones, as well as printed paper. The LSR116 is an innovative high-tech solution that takes away the high-investment pain for kiosk manufacturers.

Cadence Design Systems today introduced a qualified 32/28-nanometer reference flow targeting Common Platform technology. Cadence® collaborated closely with members of the Common Platform alliance—IBM, GLOBALFOUNDRIES, and Samsung Electronics—to develop a comprehensive flow from RTL synthesis to GDSII signoff for the advanced node, low-power high-k metal gate (HKMG) process technology.

Cadence Design Systems, Inc. today introduced the latest release of Cadence Encounter RTL-to-GDSII flow for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. Developed in close collaboration with leading IP and foundry partners and customers, the new RTL-to-GDSII design, implementation and signoff flow enables more efficient development of SoCs, meeting and exceeding the power, performance and ...

Cadence Design Systems, Inc. today announced that Samsung Electronics and Cadence have collaborated to deliver a 20-nanometer design methodology that incorporates double patterning technology for joint customer deployment and internal test chips. The collaboration between Cadence and Samsung brings new process advances for mobile consumer electronics, enabling design at 20 nanometers and future process nodes.

Cadence Design Systems, Inc. today announced that its Encounter digital and Virtuoso custom/analog design platforms achieved TSMC Phase I certification for 20-nanometer design, implementation and verification/signoff. TSMC certified the tools for 20-nanometer design rule manuals and SPICE models.

Cadence Design Systems announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor implemented using IBM’s FinFET process technology. The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nanometer FinFET-based design flow.