Innovative Silicon Unveils Z-RAM Memory Technology Breakthroughs

In the paper delivered by Nagoga, titled “Ultra-scaled Z-RAM cell,” Z-RAM cells based on Multiple-gate SOI MOSFETS (MUGFETs) with gate lengths down to 50nm and fin widths down to 11nm were demonstrated for the first time. Simulations proved that the basic operational principles are effective on Z-RAM cells with gate lengths down to 12.5nm and fin widths of 3nm.

Further analysis also shows that these devices exhibit the largest programming window (margin) ever recorded. Measured as the difference in current between STATE 1 and STATE 0, the programming window of these MUGFETs is close to 22µA.

Okhonin commented, “Even such small devices demonstrate a reliable memory effect, and the experimental data presented in the two papers indicates the excellent scalability of our Z-RAM memory devices. Furthermore, the results we demonstrated today are only achievable in floating body architectures. We believe our transistors are not only the smallest silicon dynamic memory devices ever published, but also the best performing. Moreover, at equivalent gate lengths, we demonstrated a several times larger programming window than previously published.”

Nayfeh’s paper, co-authored with ISi fellow Dr. Victor Koldyaev and titled, “A Leakage Current Model for SOI based Floating Body Memory that Includes the Poole-Frenkel Effect (PFE),” describes for the first time how the leakage current of SOI based floating body memory has been modeled and compared to experimental Z-RAM data, taking into account oxide/SOI Dit and PFE. The model has enabled the Z-RAM design team to significantly reduce the number of defects per cell, leading to an increase in retention times and a reduction in leakage current.

Jim Feldman Semico president noted, “ISi continues to demonstrate unmatched memory density and performance with its Z-RAM technology. It is also exciting to see the ongoing innovation advancing this floating body implementation.”