Memory

4 reasons to use industrial 3D TLC NAND flash as pseudo-SLC

29th July 2022
Kiera Sowery

TLC (triple-level cell) NAND flash has been making its way into industrial storage solutions for some years, thanks to its high storage density of three bits per cell. The ability to operate TLC in pseudo-single-level cell (pSLC) with one bit per cell, on the other hand, continues to carve out a niche existence.

This article originally appeared in the July'22 magazine issue of Electronic Specifier Design – see ES's Magazine Archives for more featured publications.

Nevertheless, for a vast number of applications the economic advantages of this configuration outweigh the disadvantages. In this way, the gap to true SLC memory can be bridged. Roger Griesemer, General Manager, Memory Solutions at Swissbit, provides four key arguments for using industrial 3D TLC NAND flash as pseudo-SLC.

Lifetime

While TLC NAND flash is typically only designed for 3,000 programming and erase cycles, the same memory in pSLC mode achieves 30,000 cycles with the previous flash generation and even up to 100,000 cycles with the most current flash technology.

By storing only one bit per cell instead of three, the capacity is reduced by a third or three times the amount of flash must be used. The service life, on the other hand, increases by up to 33 times. pSLC is therefore excellent for any application in which the memory is used for a long period of time and a large amount of data is written. The same is true in situations when replacement or maintenance intervals are associated with high costs or the exact write load in use is not known in advance.

The size of a page, or the minimum number of memory cells that must be programmed consecutively with every write access, is also reduced to one third with pSLC. As a result, the write amplification factor improves significantly. The combination of the extremely high number of cycles and the smaller page size results in a lifetime that is rarely exceeded by an application. Accordingly, the need for maintenance and replacement in the field is eliminated.

Reliability

To store three bits in a TLC cell, 2³ = 8 electrical voltages must be differentiated within the cells. However, because only one bit is stored in pSLC mode, the readout logic only needs to differentiate between two voltages.

The maximum voltage is limited by the type of semiconductor technology. In view of this, the distance between the eight different TLC voltages is far lower than the distance between the two pSLC voltages, resulting in more reliable data content recognition.

If, in 3D TLC, the temperature difference between writing the data and reading it out later is far apart, the controller’s built-in error correction unit may be overworked (consider the cross-temperature effect). In addition, the charge loss in memory cells is affected not only by time, but also exponentially by wear. Temperature fluctuations and charge loss can cause the readout logic to lose its ability to clearly distinguish between the eight voltage levels.

pSLC is the perfect choice for reading data reliably and at any time, especially when used under extreme temperature conditions – and even after years of high wear and tear and when subjected to strong temperature fluctuations.

Performance

Given that, with pSLC, only two states instead of eight must be programmed or recognised during reading, these processes are significantly faster. pSLC can be read twice as fast as TLC and written at six times the speed.

When reading, just one voltage level per cell must be checked with pSLC. A zero is stored in the cell if the cell voltage is above this; a one is stored if the cell volage is below. In TLC mode, only one voltage level must be checked for the first bit of the memory cell. For the second bit, two voltage levels must be checked and three voltage levels for the third bit. On average, two read accesses are therefore required, resulting in a two-fold increase in read performance.

Because a deleted cell represents a one and a programmed cell represents a zero, pSLC has a clear advantage when writing. It makes no difference how big the voltage gap is. However, because the desired voltage must be reached exactly in TLC mode, each cell must be programmed slowly in several steps.

Especially when high write speeds are required, there is usually a requirement for a long service life. The pSLC mode is the best option here as it meets both requirements

Costs

Because three times the amount of flash memory is required, switching from TLC to pSLC is associated with around three times the cost for the same capacity. If you choose true SLC, which has traditionally been used for write-intensive applications and harsh environmental conditions, you must factor in ten times the cost compared to TLC. This makes pSLC a serious alternative in terms of price.

Especially when the capacity of an SSD is secondary, and the requirement is mostly related to the TBW (total bytes written), pSLC shows its real strength. For example, in an application, log files are written in the ring buffer. In theory, 32GB of memory would suffice, but a lifetime write performance of 300 TBW (terabytes written) is required. A minimum capacity of 240GB in TLC would be required to achieve this. All requirements can be met if a 40GB pSLC SSD is used instead – and at half the cost. This is because a 40GB pSLC-SSD is equivalent to a 120GB TLC-SSD.

The optimal choice between low-cost TLC and expensive SLC memory is TLC in pSLC mode. At a fraction of the cost of true SLC NAND, the latter solution combines long lifetime, high performance, and temperature insensitivity. Therefore, Swissbit essentially offers all its products also as pSLC solutions.

TLC NAND flash in pSLC mode not only offers a long service life, but it also achieves better data retention. In closing, the following graph covers the differences between pSLC and TLC depending on wear.

Featured products

Product Spotlight

Upcoming Events

View all events
Newsletter
Latest global electronics news
© Copyright 2022 Electronic Specifier