3D flash memory provides new design flexibility
A fifth-generation BiCS FLASH three-dimensional (3D) flash memory featuring a 112-layer vertically stacked structure has been successfully developed by KIOXIA Europe. The company has plans to start shipping samples of the new device, which has a 512 gigabit (64 gigabytes) capacity with 3-bit-per-cell (triple-level cell, TLC) technology, for specific applications in the first quarter of the calendar year 2020.
The new device aims to fulfill ever-growing bit demands for a wide variety of applications, including traditional mobile devices, consumer and enterprise SSDs, emerging applications enabled by the new 5G networks, artificial intelligence and autonomous vehicles.
Going forward, KIOXIA will apply its new fifth-generation process technology to larger capacity devices, such as 1 terabit (128 gigabytes) TLC and 1.33 terabit 4-bit-per-cell (quadruple-level cell, QLC) devices.
KIOXIA’s innovative 112-layer stacking process technology is combined with advanced circuit and manufacturing process technology to increase cell array density by approximately 20% over the 96-layer stacking process.
The new technology reduces the cost per bit and increases the manufacturability of memory capacity per silicon wafer. Additionally, it improves interface speed by 50% and offers higher programming performance and shorter read latency.
Since announcing the first prototype 3D flash memory technology in 2007, KIOXIA has continued to advance development of 3D flash memory and is actively promoting BiCS FLASH to meet the demand for larger capacities with smaller die sizes.
Fifth-generation BiCS FLASH was developed jointly with technology and manufacturing partner Western Digital Corporation. It will be manufactured at KIOXIA’s Yokkaichi Plant and the newly built Kitakami Plant.
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