Oasys Design Systems Announces Register Retiming Capability

“This new capability from Oasys is part of our ongoing commitment to our customers to provide the best possible QoR for SoC and ASIC design teams,” said Scott Seaton, President and CEO at Oasys. “By providing massive RTL capacity, up to 10 times faster runtimes, physical awareness, and now improved QoR, Oasys is empowering design teams to address the increasing demands of today’s SoCs and ASICs.”

Especially important in graphics, networking, and mobile applications, register retiming is a technique of moving the structural location of registers in a digital circuit to improve its performance, area, and power characteristics in such a way that preserves its functional behavior at its inputs and outputs. The RealTime synthesis engine automatically moves registers through combinational logic to balance and optimize the delay across each stage of a pipeline. RealTime synthesis provides an integrated equivalency checking capability that automatically verifies the retimed gate-level logic is correct functionally. A key advantage of the retiming capability within the Oasys RealTime synthesis engine is that the results more accurately correlate to the results achieved after placement and routing because of its physically-aware synthesis capability.

“With the increased adoption of Oasys RealTime by SoC and ASIC designers worldwide, we are working with more and diverse customer applications.” said Paul van Besouw, Oasys CTO. “Register retiming capability is critical for SoC and ASIC designers who need to minimize power and area while simultaneously maximizing circuit performance.”

Register retiming is available immediately as a standard feature in the Oasys RealTime Explorer and Designer products.