Saelig Introduces Powerful USB Embedded Development Tool
Saelig announced the availability of GP-24100 - a PC-controlled USB 2.0 high speed device featuring ADWG (Arbitrary Digital Waveform Generator), and logic analyzer capabilities. It enables the stimulation and analysis of digital interfaces, streaming data to/from a PC to 16 data lines at up to 10MHz, with 6 additional control lines for repetitive sequence generation, in/out clocking or trigger definition. Electronic engineers now have an easy-to-use tool to access electronic systems from their favorite workstation,offering a significant productivity gain for system-on-board development.With
The supplied 8PI Control Panel Software offers instantly-usable graphical scripting (TCL/tk) and programming (C/C++) interfaces to automate tasks and bridge between programming environments and hardware prototypes. 8PI software allows you to define I/O clocks, repetitive sequences, and trigger patterns; and to automate tasks or build custom applications, you can use the TCL scripting environment, or C, C++ DLLs. It can also set repetitive and cumbersome lab tasks such as controlling a DAC (digital-to-analog converter), sending a stimulus to a custom IP block in an FPGA, or to create an arbitrary stimulus and collect results.
With its ADWG / Pattern Generator mode of operation, GP-24100 allows you to generate extended depths of arbitrary digital stimuli, directly from a PC through a USB connection - create16 bit-wide arbitrary patterns at up to 100 MHz, using the huge 8MB internal memory buffer.
GP-24100’s Analyzer modeof operation transforms the compact test box into a simple logic analyzer to collect and analyze digital data, sampling 16 bits at up to 100 MHz and storing data in 8 Mbytes of internal memory.
There are many ways of interacting with GP-24100: Windows GUI, C/C++ and TCL/tk. This essential developer tool is suited to a wide range of applications, including: JTAG (IEEE 1149.1) access, logic/state analysis/data logging, Arbitrary Digital Waveform Generator/pattern-generator, serial protocol access, FPGA/CPLD serial or parallel configuration, parallel protocol access (up to 6 control lines/16 data lines), bus-master emulation, SRAM, flash interface, system debug and system prototype access, bidirectional protocol analyzer, IP prototypingand evaluation, recorder/player tools, ADC/DAC test and control, pattern waveform generation, etc. Optional extras include SPI and I²C bus exerciser / analyzer modes of operation