Design

FPGA-based reference design doubles NAND Flash life

1st July 2015
Nat Bowers
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Based on the company's Arria 10 SoCs, a storage reference design that doubles the life of NAND flash has been introduced by Altera. It can also increase the number of programme-erase cycles by up to seven times compared to current NAND flash implementations.

The reference design includes an Arria 10 SoC with an integrated dual-core ARM CortexA9 processor, in an optimised, cost-effective, single-chip solution, leveraging an SSD controller from Mobiveil and NAND optimisation software from NVMdurance. This reference design provides improved performance and flexibility in NAND utilisation while reducing the cost of the NAND array by increasing the lifetime of data centre equipment.

Robert Pierce, Senior Marketing Manager, Compute and Storage Business Unit, Altera, commented: “Until now, it was not possible to make the economics of FPGA flash storage work. Our Arria 10 SoC-based solution will make architects rethink how storage is deployed in the cloud and in high-performance computing systems - opening up new ways to innovate and extend a company’s investment, while providing the fast time-to-market that can be a competitive differentiator.”

Using FPGAs with integrated hard processor systems, designers can quickly take advantage of the cost savings offered by next-gen NAND devices while retaining the flexibility to customise a solution that maximises the performance, durability and storage capacity of their system. This storage solution implements Mobiveil’s Universal NVM EXpress (UNEX) controller, a configurable controller for PCIe-based SSDs and NVMdurance’s NAND flash optimisation software in an Arria 10 SoC, enabling data centres to leverage the most advanced 3D NAND technology without the long design cycles required with ASIC designs.

In this reference design, Mobiveil’s controller supports multi-core architectures, enabling threads to run on each core with their own queue and interrupt without any locks required. NVMdurance’s NAND flash optimisation software constantly monitors the condition of the NAND flash and automatically adjusts the control parameters in real time, greatly extending the flash system’s endurance. The Altera reference design also features end-to-end data protection, encryption and compression and optimises throughput and power consumption, all in a small silicon footprint.

“An FPGA-based storage system provides hardware offload functions and makes specification updates easier to execute than flash storage designed with an ASIC SoC. The Arria 10 SoC, with its embedded ARM cores, PCI Express Gen3 and DDR4 interfaces, along with our SSD controller and IP from NVMdurance, squarely delivers what data centre architects need in a NAND storage solution - improved power, scalability and total cost of ownership,” said Ravi Thummarukudy, CEO, Mobiveil.

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