Audio solutions for entry level infotainment systems
An entry level infotainment processor for display audio, radio/audio and other cost sensitive in-vehicle segments has been added to the “Jacinto 6” family of System-on-Chips (SoCs) from Texas Instruments.
The new DRA71x processor, “Jacinto 6 Entry,” is developed on the same architecture as other “Jacinto 6” devices, enabling automotive manufacturers to scale their investment without additional R&D or significant bill of material (BOM) increases.
The scalable performance within the DRA71x allows developers to target specific performance for their applications and leverage headroom using higher performance variants, if required, without software modifications or hardware changes.
The DRA71x “Jacinto 6 Entry” processor is the lowest cost, feature optimised member of the “Jacinto 6” family, extending the DRA72x “Jacinto 6 Eco” processor into more cost sensitive applications and systems. TI’s DRA71x delivers car manufacturers with integration of automotive features and interfaces for a processor at the entry level of infotainment systems. As a result, the BOM is reduced and software investments leveraging the “Jacinto 6” family are protected, including high level operating systems such as Linux, QNX and Android on ARM Cortex-A15 cores, as well as DSP and other cores.
TI’s DRA71x delivers an optimised set of performance and features to address the display audio and entry infotainment segments including:
- An integrated TMS320C66x DSP for software defined radio (SDR) integration, audio/speech processing, noise suppression and camera/imaging processing.
- Video decode/processing capability with 1080p60 decoding at greater than 30Mbps to support concurrent high quality smartphone screen replication (including 3D maps) and on-board video acceleration for multi-media playback.
- High memory bandwidth at 32-bit DDR3 EMIF at 667MHz for a best in class HMI, HD display support and improved auto-concurrencies.
- Integrated video ports for integrating support for NHTSA required rear visibility technology or other camera applications.
- ARM Cortex-M4 cores as auxiliary processors to offload high interrupt load tasks from the main ARM core and provide physical separation between High Level Operating System (HLOS) and real time operating system (RTOS).
The “Jacinto 6” family of processors is built on the same architecture, offering software and hardware compatibility with the broadest array of highly scalable ARM Cortex-A15 cores for automotive applications.