Application Notes
Impact of TMS470R1x ZPLL Jitter on CAN Communication (Rev. A)
Texas Instruments
Published : 27 Mar 06
Description
The first section describes the impact of the clock jitter introduced by the analog phase−locked loop module (ZPLL) on the system clock (SYSCLK) and the peripheral clock (ICLK). In the second section the resulting impact on the CAN communication is explained.
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