nergy-efficient data processing will be vital for a wide range of emerging applications from Body Area Networks to building automation and equipment monitoring. Reducing active power consumption and standby leakage are thus increasingly important considerations for digital design,” said Harmke de Groot, Program Director at Holst Centre/imec. “Yet much of the industry’s research is still aimed at improving performance rather than increasing battery lifetime by higher energy efficiency. At Holst Centre, we focus on low power and low voltage to enable battery-powered and energy scavenging smart devices.”
The new energy-efficient processor platform is customized for biomedical applications such as ECG and EEG monitoring. This was realized by creating an interface architecture around a general-purpose processor core to enable ultra-low voltage operation and automatic scaling of performance to improve energy efficiency, plus in-situ monitoring to guarantee reliability and high yield.
One of the key developments was the ability to reduce the operating voltage while delivering enough performance to meet application needs, and maintaining that performance over a range of operating voltages and temperatures. That was achieved by forward biasing the transistors within the processor, allowing it to operate at voltages just above the threshold for the CMOS process used. The operating voltage can be adjusted between the processor’s nominal voltage of 1.1 V and a minimum voltage of 0.4 V depending on the current performance requirements.
Natural variations in manufacturing processes can lead to voltage fluctuations when a processor is being used. At near-threshold voltages, these fluctuations can be enough to stop the processer working. To avoid this and ensure reliability, the team connected “canary flip-flops” to the most timing-critical parts of the processor. These are designed to fail before the processor’s circuits do and can be monitored – allowing the operating voltage to be scaled up before noise affects the processor. In addition, automatic bias control eliminates the usual voltage drop across the power switches that control the processor, further enhancing energy efficiency and reliability under near-threshold conditions.
To reduce energy consumption even further, the interface can control the state of individual components on the chip separately, for example turning off the processor core or reducing the voltage in the memory when these components are not required. The software interface can also dynamically switch the processor between various performance modes, optimizing the number of active functional units in the core to suit the algorithm being performed. Unused functional units are switched off to reduce power consumption.