e Superjunction MOSFETs have enabled new levels of efficiency in power applications ranging from AC-DC power supplies and lighting ballasts, to micro inverters in solar power installations, the imperative to reduce the power consumed by electrical equipment is forcing increasingly aggressive revisions of eco-design guidelines such as Energy Star and the European ErP directive.
The typical scope of such standards is increasing to include more types of end-user products and to set specific targets for energy efficiency in all operational modes. The latest Energy Star targets, for example, limit power consumption of LCD televisions according to screen size. Minimum targets for operating efficiency are also being introduced, as evidenced by schemes such as Energy Star 80 Plus.
Clearly, equipment designers can — and must — employ various power-saving techniques throughout the design of a given application, to satisfy these standards. The main power supply circuitry represents a key area where energy is lost, since all of the power drawn by the application must first pass through the PSU. Increasing the efficiency of power supplies operating from AC line voltages in equipment such as desktop or notebook PCs, large-screen televisions and home appliances is therefore a major target for the electronic design community.
Other applications under the efficiency spotlight include energy-saving lighting such as CFL ballasts and high-power LED drivers. In addition, as interest in solar electricity generation continues to grow, efficient power conditioning and conversion is vital to maximise yield from the solar modules. This calls for very high efficiency in the micro-inverters used to produce high-quality sinusoidal AC power at the local AC line voltage.
MOSFETs are the power switch of choice in most of these applications, offering advantages such as simple gate-drive circuitry and relatively high efficiency in relation to voltage rating. Devices with a voltage rating in the range of 5-600V are generally required for 250V AC line-powered applications, to provide a suitable safety margin against potentially damaging high-voltage transients. As designers strive to satisfy successive generations of eco-design standards and deliver ever more efficient end products, there is intense interest in achieving continued improvements in efficiency and performance in MOSFETs at this voltage rating.
The efficiency of switching power converters such as switched-mode power supplies (SMPS) and DC-AC inverters is heavily dependent upon the loss mechanisms in the main power switch, which may comprise a single MOSFET or a MOSFET bridge depending on the application. Successive generations of power MOSFETs have sought to minimise conduction losses by reducing the device’s on-resistance (RDS(ON)). Switching efficiency, on the other hand, is improved by minimising parasitic capacitances around the gate, source and drain that, combined, constitute the MOSFET’s effective input and output capacitance. In addition, the gate charge (QG) determines the energy the gate driver must supply to switch the device. A low gate charge allows designers to use high switching frequencies, which permits the use of small external filtering components in order to minimise solution size and cost.
Conventional high-voltage MOSFET technologies face limitations, both in terms of reducing RDS(ON) as well as improving switching performance by reducing capacitances and gate charge. In high-voltage MOSFETs the resistance of the drift region is the dominant constituent of the device on-resistance, but the dimensions and doping of this region must be tightly controlled to achieve the desired breakdown voltage rating. Hence there is a natural limit, termed the silicon limit, beyond which the MOSFET’s on-resistance for a given die area cannot be reduced without also reducing breakdown voltage. Although increasing the die area can reduce on-resistance, this comes at the expense of greater cost and a larger package size.
For a given MOSFET technology, measures taken to reduce the on-resistance tend to increase the gate charge, hence forcing a compromise between conduction and switching performance. This compromise is expressed in the MOSFET’s Figure of Merit, typically expressed as:
RDS(ON) x QG
Note that the figures multiplied should be as measured under conditions of identical temperature, gate-source voltage and drain-source voltage.
Beyond Silicon's Limit
As far as conventional MOSFET technologies are concerned, device designers have little opportunity to improve upon the figure of merit for a given device type. This forces a compromise between conduction performance and switching performance.
Superjunction MOSFET technology has a fundamentally different structure that breaks through these limitations. Rich doping of the N region reduces resistivity, resulting in significantly lower on-resistance than is possible in a conventional MOSFET. To achieve the desired breakdown voltage, this region is bounded by adjacent deep P-type trenches. This produces a column structure as shown in Figure 1b, compared to the conventional MOSFET structure illustrated in Figure 1a.
Figure 1 : Conventional MOSFET structure (a) and basic superjunction MOSFET structure (b)
Superjunction MOSFETs have been available for a number of product generations. Evolution has delivered improvements in on-state resistance by reducing the pitch and increasing the aspect ratio of the P- and N-type columns. Multi-axial processes have proved successful in producing columns of close pitch and high aspect ratio. This approach utilises repeated stages of ion implantation and buried n-type epitaxial growth. Toshiba has used this process in its previous generations of DTMOS (dynamic threshold MOSFET) superjunction devices. One limitation of this approach is that the number of process steps must be increased to achieve each successive improvement in on-state resistance. This tends to increase production cost.
A new technique is required to further this path of development, fabricating columns at closer pitch and higher aspect ratio, in order to deliver cost-effective devices offering even better on-state resistance than the previous generation. Deep trench filling enables superjunction MOSFET designers to achieve these goals. The process comprises deep trench etching followed by P-type epitaxial growth, eliminating a large number of process steps and so providing a cost-effective route to improving on-state resistance. Figure 2 compares the profile of the P-type trench achievable using deep trench filling, with that produced by the multi-epitaxial process.
Figure 2: Superjunction structures showing multi-epitaxial process and trench profile using Deep Trench filling
Toshiba has used deep trench filling in its DTMOS IV fourth-generation superjunction process.This has allowed closer trench pitch compared to the third-generation (multi-epitaxial) process, ultimately yielding 30% better on-state resistance per die area (specific on-resistance). DTMOS IV MOSFETs claim the lowest specific on-resistance in the entire 600V class, and deliver the lowest RDS(ON) among competing devices in each power-package type.
Switching And Noise Performance
Although narrowing the column pitch holds the key to minimising specific on-resistance, it also has the effect of reducing the gate charge, QG. Care must be taken to avoid excessive reduction of QG, as this can allow high dVDS/dt when switching leading to an increase in emission of electromagnetic interference (EMI). On the other hand, a low value of QG helps to reduce losses in the gate-driving circuitry and also allows designers to specify a lower output gate-driving device and thereby save system cost and size. DTMOS IV has an optimised gate structure designed to achieve RDS(ON) x QG and RDS(ON) x QGD figures of merit comparable to those of the preceding DTMOS III generation.
DTMOS IV devices can be offered in an expanded range of industry-standard packages, the largest of these packages, the TO-3P(L), allows the lowest RDS(ON) in the industry, at 0.018Ω (18mΩ). At the other end of the spectrum, the fourth generation technology enables vendors to offer a 600V device in the DPAK package, with RDS(ON) of 0.9Ω.
Fully isolated TO-220SIS package solutions, using Toshiba’s established copper connector technology, will offer the finest split of RDS(on) from 0.9Ω to the best in class performance of 0.065Ω, in this form factor. It is worth noting that D2PAK and I2PAK are currently popular package choices in applications such as solar micro inverters, where 600V fourth-generation superjunction MOSFETs can offer RDS(ON) from 0.19Ω to 0.16Ω. For mainstream industrial solutions TO-220 solutions have RDS(ON) ratings ranging from 0.38Ω to 0.088Ω.
The deep trench filling process has increased the scope for MOSFET designers to minimise on-resistance per area by creating deeper, narrower P-type trenches of more controlled and uniform shape. Further development of deep trench filling should provide extra freedom to reduce device on-resistance and increase breakdown voltage above 600V, while maintaining control over switching performance by optimising gate charge and parasitic capacitances.
In the nearer term, device designers can take advantage of the savings in silicon area to introduce fourth-generation MOSFETs offering an integrated Fast-Recovery Diode (FRD). Such devices can be expected to enter the market very soon.