Designing the next smart and lower-power applications

18th July 2015
Posted By : Caroline Hayes
Designing the next smart and lower-power applications


Dung Dang, Texas Instruments explains why Texas Instruments introduced the MSP432 MCU to address the power-saving issues while raising the bar for high performance on ultra-low-power MCUs.

As the electronics industry continues to make things smaller and smarter, especially with the IoT (Internet of Things), embedded applications are becoming more intelligent and connected at a fast pace.

Developers are challenged with packing more performance into energy-constrained devices. The MSP432 microcontrollers integrate a number of power enhancements which include lower active power consumption, low power (LP) mode current consumption and more efficient peripherals with lower current consumption. Additionally, they provide a number of options and power configurations that enable developers to further tweak and optimise the power consumption for specific applications.

This article highlights a few of these design techniques implemented in the MSP432 MCU platform to help developers add more MHz and reduce mA at the same time.

Maximising core logic voltage

Like many other modern MCUs, these MCUs employ a secondary core voltage (VCORE) for its internal CPU, memory and digital operation in addition to the primary one applied to the device (VCC). VCORE is usually generated from an LDO with programmable output from two pre-defined voltage levels and each level is restricted to particular maximum operating frequencies. This provides programmable dynamic voltage frequency scaling (DVFS), which essentially throttles the power output when the device only needs to operate at lower frequency.

Taking a leap beyond DVFS, the MCUs further enhance the VCORE concept by introducing an additional regulator, in this case a DC/DC, to completely maximise power saving in active modes. Unlike an LDO, which generates a voltage rail from another by dropping the extra voltage across a linear, effectively passive, power-consuming element, the DC/DC efficiently generates the VCORE rail using active elements. After accounting for some efficiency loss, the DC/DC typically has efficiency in the range of 75 to 90% for moderate to maximum loads, ultimately yielding power saving of up to 45% compared to the LDO regulator. This is also dependent on the gap between supply and core voltages.

Table 1 shows the current consumption comparison between DC/DC and LDO when the system operates at 24MHz and 48MHz.

 Table 1: A comparison of current consumption between LDO and DC/DC regulators at two frequencies

Table 1: A comparison of current consumption between LDO and DC/DC regulators at two frequencies

The LDO is not without its own advantages, including faster wake-up time as well as the ability to scale the output strength, which is useful to drive down the quiescent current, particularly in standby modes. The MSP432 MCU platform provides developers with the flexibility to dynamically select and configure either or both regulators at runtime to cater specifically to the application, which might have different sets of power requirements at different times.

Power gating

A more powerful CPU, higher memory density and more features all translate into higher gate count and leakage current. Coupling with smaller geometries being invested into for a higher performance MCU, this exacerbates the leakage current issue, especially in standby mode. This feature further drives the need to optimise current consumption in standby mode.

The MSP432 MCUs introduce two low-power techniques to combat this issue. Firstly, the MCUs aggressively apply a power-gating methodology, where anything non-essential for RTC standby mode is completely power-gated off and consumes zero power from the system. Secondly, a number of slow-speed, but low-leak transistors are used specifically for peripherals operating in the low-power domain in standby mode, where low-leakage, not speed, is a priority.

Flash buffer

The MSP432 flash controller comes with a configurable 128bit flash buffer that can help reduce the number of direct flash accesses or improve the effective flash speed when the CPU operates faster than the native flash speed (i.e. reducing the effective wait-states). This feature is particularly useful when executing a stretch of linear code with high continuity and minimal jumps or branches. Developers also have the flexibility to turn off the buffer and reduce the power consumption when it is not needed (e.g. CPU frequency equal to or less than flash speed). Two run-time flash access benchmark registers are also implemented to help developers assess the continuality and frequency of flash accesses in order to determine the optimal CPU speed, flash speed as flash buffer configuration.

The MSP432P4xx family provides a number of low-power operating modes that originated in the MSP430 devices, including LPM3, LPM4, LPM3.5, and LPM4.5. Similar to earlier MSP devices, these low-power modes on MSP432P4xx consume extremely little power. In addition to the traditional MSP low-power modes, the MSP432P4xx family introduces another class of low-power modes that can provide additional power saving: low-frequency power modes. The low-frequency modes are low-power, low-frequency options that can be used in conjunction with both active and LPM0 modes. In these low-frequency modes, memory and peripherals can execute at maximum speed of 128kHz. The regulator can reduce the drive strength to supply minimal current to drive the entire low-frequency system. As a result, the device’s total current consumption can be as little as 80µA when using these modes.

Driver library in ROM

In addition to flash, the MSP432P4xx MCU also provides ROM as a second, non-volatile memory option. The ROM can provide tremendous benefits over flash memory when used properly. For example, ROM execution yields both higher performance (zero wait state access to ROM at maximum CPU frequency) and better power consumption (40% lower than flash). Both of these performance increases i.e. faster execution time and lower power consumption, directly result in minimising the energy consumption of the device.

Figure 1: Determining the optimal MSP432 MCU system options for ULPBench

Figure 1: Determining the optimal MSP432 MCU system options for ULPBench

The most commonly used software on any MSP432 application is the highly abstracted and robust Driver Library. This is optimised and packed into the ROM. Developers can directly benefit from the performance gain and power saving every time they need to manipulate the device peripherals and can free up to 25kbyte of space normally needed in flash.

Total power saving

An ecosystem also provides a set of ultra-low-power tools and software that developers can use to further optimise the application power consumption.

The final low-power optimisation procedure is to determine the best combination of low-power options that work for a specific application. Figure 1 demonstrates how the low-power features could be used together to help MCUs ultimately achieve the highest ULPBench score possible for a Cortex-M4F MCU, using the ULPBench application. Once the ideal power and system configuration was determined, in this specific case using the DC/DC regulator, running at 24MHz, flash buffer enabled, maximising ROM usage, the last round of system optimisation resulted in the final EEBMC-certified score of 167.4.

Similarly developers can tweak the power to meet the specific requirements of their applications. A number of ultra-low-power coding and debugging tools, including the company’s ULP Advisor and EnergyTrace+ technologies, are also available to optimise process and combination of settings on the MCU. A careful balance enables developers to create the next ultra-low-power and high performance embedded applications.

Starting with a well-designed embedded system using silicon and hardware knowledge, embedded developers can then take advantage of static code analyser tool, such as ULP Advisor, to further identify areas in the code to optimise for execution time and to reduce power consumption.

Next, during debug phase, developers can use EnergyTrace technology to construct an energy profile of the application and correlate critical energy consumption spikes to areas in the code. This allows developers to identify high-energy components in the configuration or software for further power improvement.

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