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SH-Mobile APE4 breaks into GHz realm to open up an entirely new user experience and set the pace for true multimedia convergence

26th November 2009
ES Admin
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Renesas Technology Europe today announced that it is sampling the SH-Mobile APE4 (product number: R8A73720), an ARM Cortex-A8 based Application Processor Engine running at a speed of more than 1GHz, targeted for next generation mobile phone and mobile device implementations. With the integration of various dedicated processing engines the device features ultimate multimedia capabilities, such as 1080p full HD video recording/playback at 30fps, and high speed 3D graphics rendering for sophisticated 3D UIs and an advanced gaming experience. Leveraging on Renesas' market proven Image Signal Processor (ISP) technology, the SH-Mobile APE4 provides a state-of-the art 16Mpixel ISP for best visual quality while supporting full HD1080p movie processing. Fabricated in Renesas' optimized 45nm low power process and integrating a wealth of new and innovative power saving schemes, it exceeds the stringent power budget requirements of mobile phones.
With broadband wireless access like UMTS/HSPA or LTE, customers can have the internet at their fingertips wherever and whenever. Access to music, videos and games with mobile phones becomes as simple as it became on the PC a few years ago says Carsten Wild, Marketing Manager Application Processor Platforms, Renesas Mobile Platform Center. Renesas has developed the Application Processor Engine, SH-Mobile APE4, as the first device in a new class of application processors to offer an entirely new user experience on mobile computers and to solve the conflicts around creating an exciting multimedia experience within the low power budget of mobile devices.

The SH-Mobile APE4 is based on an ARM® Cortex(tm)-A8 core operating at a speed of more than 1GHz. Leveraging Renesas' vast experience of highly integrated SoC systems, a competitive SoC process and an innovative design architecture, this device aims for one of the industry's most efficient ARM® Cortex(tm)-A8 implementations providing amble processing performance for next generation applications while pursuing the ultimate low power consumption that enables an entirely new user experience on mobile devices.

For the ultimate multimedia experience the SH-Mobile APE4 incorporates a variety of dedicated processing engines. An integrated ISP supports 16M pixel still images and full HD 1080p movie images. A dedicated high-performance multi-codec video processing unit for ultra-low power video processing enables the device to support full HD1080p30 multi-standard video use cases such as encoding (recording) and decoding (playback) of full HD video (1920 × 1080 pixels) at 30 frames per second (fps). Combined with various multi-phased visual engines, such as IP for edge enhancement or median filtering, the realization of High Quality HD images and videos reaches levels which consumers will not have experienced before on mobile devices.

To support high speed 3D graphics rendering for sophisticated 3D UIs and an advanced gaming experience, the device is equipped with a powerful POWERVR SGX 3D graphics engine, licensed from Imagination Technologies, supporting graphic APIs such as OpenGL ES1.1/2.0 and Open VG. To round off the multimedia experience, the SH-Mobile APE4 also incorporates a highly sophisticated audio subsystem enabling well over 100 hours of audio playback on a standard mobile phone battery.

For design flexibility and reduced system BOM, the SH-Mobile APE4 includes a wide variety of on-chip peripheral functions and connectivity interfaces. This includes two USB 2.0 Host/Function modules (with high-speed data transfer mode support), three SD host controllers with support for high-speed data transfer mode and a 24-bit TFT color LCD controller supporting up to WXGA+ display sizes. Furthermore a PAL/NTSC encoder and an HDMI transmitter are integrated together with a complete HDMI v1.3a & CVBS TV-Out interface.

The SH-Mobile APE4 is packaged in a 0.4mm pitch, 12mm x 12mm BGA package that allows package-on-package vertical stacking of low power, multiple chip package (MCP) memory such as LP-DDR2, greatly reducing the overall footprint of the memory and processor combination.

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