Renesas Technology's SH77650 SoC for automotive image recognition processing

The SH77650 provides the same image recognition functions as Renesas’ existing SH7774 high-performance SoC product for car navigation systems. Developed as a dedicated image recognition processing LSI device, the new SoC product delivers a superior cost-performance through optimized functionality and performance.

The device features image recognition processing intellectual property (IP) from Hitachi, Ltd. This IP covers specialized hardware that performs the processing necessary to recognize road conditions based on image data captured by a camera or similar device. It enables multiple external environment recognition programs to run simultaneously and in real time. These programs can perform tasks such as roadway lane recognition or detection and tracking of leading vehicles. This capability makes it possible to realize sophisticated functions to increase safety when driving a vehicle. In addition, an image recognition library with approximately 200 functions is provided to facilitate the development of image recognition applications. It is also possible to use image recognition applications originally developed for the SH7774 with the SH77650.

The SH77650 incorporates the SH-4A, the top-end CPU core in the SuperH Family. At its maximum operating frequency of 300 MHz its processing performance is 540 MIPS (million instructions per second). The on-chip floating-point processing unit (FPU) also operates at a maximum of 300 MHz. The FPU supports single- and double-precision calculations, delivering a maximum operating performance of 2.1 GFLOPS (giga floating-point operations per second) in single-precision mode.

A variety of modules, suitable for automotive image recognition applications, are provided. These include, in addition to an image recognition processing accelerator, video input interface and display functions, a dedicated DMA controller, timers, a serial communication interface, and a CAN interface for in-vehicle LANs. Screens up to a maximum WVGA size, 850 x 480 pixel) are supported.

In addition, there is an on-chip bus arbitrator circuit that sets the priority of attempts by the modules to access the bus. This circuit supports three access priority levels and makes it possible for multiple internal modules to access external memory efficiently. The user can change the priority levels in order to meet the requirements of the CPU or image processing performance. In this way the maximum performance can be achieved to match the system configuration and functions.

Furthermore, a 32-bit dedicated bus is provided as an external bus allowing connection to high-speed DDR1-SDRAM (Double Data Rate 1 - Synchronous DRAM), and a 32-bit expansion bus enables connection to flash memory or SRAM.

The package used is a 376-pin BGA (19 mm × 19 mm).

Available development tools include the E10A-USB emulator, which connects to a host PC via a USB bus. It also provides on-chip debugging functionality, allowing real-time debugging at the SH77650’s maximum operating frequency.