Intersil’s 12-Bit 500MSPS A/D Converter Delivers Industry’s Lowest Power Consumption, Most Compact Package

4th August 2010
ES Admin
Intersil introduced a family of new 8-, 10- and 12-bit 500MSPS analog to digital (ADC) converters. The lead product, the 12-bit, ISLA112P50IRZ 500MSPS converter, features power consumption of just 468 milliWatts - five times lower than any competing 12-bit 500MSPS ADC.
The lower power consumption enables system designers to integrate multiple ADCs in a single system without the thermal challenges normally associated with using high-speed ADCs. Moreover, the ISLA112P50’s low power consumption also benefits designers targeting portable or battery powered applications by helping extend battery life without sacrificing performance.

The ISLA112P50 is the latest in Intersil’s expanding family of high-speed, low-power ADCs. Developed for broadband communications, radar, light detection and ranging (LIDAR), and data acquisition systems, the new converter is being built using Intersil’s proprietary FemtoCharge technology on a standard CMOS process. The ISLA112P50 uses a pair of time-interleaved 250MSPS ADCs to generate its 500MSPS sample rate. The new IC also features the patented Intersil Interleave Engine (I2E) technology, which performs automatic fine correction of offset, gain and sample time skew mismatches between unit ADCs to ensure high performance.

The converter’s dynamic performance and specifications are optimal for targeted applications such as high-end data acquisition systems. Analog input bandwidth is 1.15GHz. Signal-to-noise ratio (SNR) is 65.8dBFS and SFDR is 80dBc for an input frequency of 190MHz. The device incorporates nap/sleep modes, and digital output data is available in either LVDS or CMOS formats, increasing design flexibility.

A synchronous clock divider reset aids in time alignment of multiple devices, a critical feature in certain systems, for interleaving at the board level or simultaneous sampling. Specified min/max digital interface timing with respect to the ADC input clock improves system reliability by allowing designers to close timing and select the most cost-efficient FPGA that meets the timing requirements.

The ISLA112P50 also is easily configured using a serial peripheral interface port, which is able to control the interleave correction circuitry, allowing the system to issue continuous calibration commands and configure dynamic parameters.

The 12-bit ISLA112P50 is part of a family of pin-compatible converters that includes the 10-bit ISLA110P50 and the 8-bit ISLA118P50. All are available in a space efficient 72-pin QFN package that is only 10x10mm, which is 49 percent to 77 percent smaller than competing parts.

Flexible Evaluation System Ready
Intersil also is making available the industry’s most flexible evaluation system, developed to enable designers to analyze performance in both time and frequency domains. The system features a modular design with one motherboard that supports multiple ADC families. Matlab code is available for hardware-in-the-loop analysis and can capture greater than 1 Megasample in a single, contiguous capture. Users can download captured data to standard CSV files to apply specialized post processing.

Pricing and Availability
The pin-compatible ISLA118P50IRZ, ISLA110P50IRZ and ISLA112P50IRZ are currently in stock and are in full production. Prices in 1,000- piece quantities range from $36 to $125 depending on the selected resolution. The evaluation kit, including complete support from Intersil, is available for prices starting at $300 each. For a full list of features on these products or additional information on Intersil ADCs, visit

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