Stacked nanowire gate-all-around transistors for N3 and beyond

11th December 2018
Source: IMEC
Posted By : Alex Lynn
Stacked nanowire gate-all-around transistors for N3 and beyond

At this week’s 2018 IEEE International Electron Devices Meeting (IEDM), imec, the research and innovation hub in nano-electronics and digital technology, reported significant progress in process enabling the introduction of gate-all-around (GAA) transistors with vertically stacked nanowires and nanosheets for the N3 technology node.

Results reportedly include improved Si GAA devices, better understanding of strain engineering in Ge nanowire pFETs, and a comprehensive understanding of reliability and degradation mechanisms of nanowire FETs.

GAA MOSFETs are promising candidates to extend the gate length and gate pitch scaling beyond what is possible with FinFETs. The use of lateral nanowires or nanosheets has the advantage of a process flow that is not so disruptive compared to FinFET processing. And by stacking the nanowires or nanosheets, the concept allows maximising the drive current for a given footprint. At last year’s IEDM, imec presented first functional circuits; today the research centre presents three studies that include process optimisations and a better understanding of strain engineering and reliability in GAA MOSFETs.

A first study shows how process improvements may significantly reduce the nanowire size and improve the shape controllability without degrading the electrical performance. With these improvements, imec made Si GAA devices with a reduced vertical spacing, a large improvement of Ion/Ioff performance and short channel margin for both nMOS and pMOS devices. The results were demonstrated by an improvement of the gate delay from 24ps down to 10ps in a ring oscillator.

A second study compared germanium nanowire pFETs with germanium FinFETs and reveaed the marked advantage of the former, mainly due to a more optimal strain engineering. The original demonstration of this work (IEDM 2017) has received the Paul Rappaport Award (presented at the plenary session at IEDM 2018, Monday December 3rd). Last, an extensive mapping of n-, p- Si and p-Ge nanowire FETs in the entire bias space allowed to characterise the various degradation metrics and reveal multiple active degradation mechanisms.

“Gate-all-around nanowire transistors are promising candidates to replace FinFETs for nodes beyond N5, and this without too much disruption,” commented Naoto Horiguchi, distinguished member of the technical staff at imec. “These new results further optimise the processes to realise these transistors and provide us with more understanding, e.g. on optimal strain engineering and degradation mechanisms.”


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