Synopsys and Helic together deliver analogue and RF custom design flow

18th December 2017
Posted By : Lanna Cooper
Synopsys and Helic together deliver analogue and RF custom design flow

Synopsys and Helic has announced that the companies have collaborated to integrate Helic's VeloceRF RF device synthesis, RaptorX EM modeling and Exalto EM parasitic extraction and signoff tools with Synopsys' Custom Design Platform. The result of the collaboration is a complete solution for electromagnetic-aware (EM-aware) layout and analysis of mixed-signal, analogue, and RF designs.

"At Asahi Kasei Microdevices Corporation (AKM) our custom design flow is based on Synopsys' Custom Compiler tool and we use Helic's RF circuit design and verification solution," said Koji Tomioka, General Manager of AKM. "We believe this unified EM-aware flow will help our engineers accelerate their pace of innovation and increase the robustness of their designs."

The Synopsys/Helic EM-aware flow provides a GUI within Custom Compiler for users to generate DRC-clean layouts of single- or multi-inductor spiral structures with VeloceRF. VeloceRF also creates schematic symbols and simulation models that are ready for use in Custom Compiler, and LVS rules for verification of the generated devices with IC Validator.

The flow also includes a tight integration of Helic's RaptorX, for in-design analysis of EM effects during layout. Early awareness of EM effects helps reduce iterations during signoff verification. The Exalto EM parasitic extraction engine works with Synopsys' StarRC tool to provide a complete RLCK parasitic netlist that is ready for RF simulation.

Synopsys Custom Design Platform users can perform frequency-domain simulation of their circuits with HSPICE technology and analyse the results with the Custom WaveView solution.

"Designers of chips operating at high data bandwidth and frequencies need detailed parasitic extraction and EM-aware analysis early and throughout the physical design flow," said Yorgos Koutsoyannopoulos, CEO of Helic. "Bringing our EM-aware modeling, analysis, and signoff technology into the Synopsys Custom Compiler environment will enable our mutual customers to avoid excessive margining and guardbanding and reduce the risk of silicon surprises."

"As the Custom Compiler user community continues to grow, we are aggressively expanding our third-party ecosystem to support it," said Bijan Kiani, Vice President of Product Marketing at Synopsys. "With this latest collaboration, we have worked closely with Helic to deliver a strong solution for EM-aware custom design to our mutual customers."

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