Imec and Holst Centre realized this ultra-low power ADC with record performance by using a unique concept that combines a successive approximation (SAR) architecture working completely in the charge domain with an asynchronous controller. By doing all the charge redistribution passively, the power consumption of the SAR ADC is already drastically reduced compared to conventional SAR ADCs. An asynchronous controller is implemented to further minimize the power consumption and to allow operation on a single external sampling clock. This asynchronous implementation thus has no clock-driven precharge phase but instead self-synchronizes the various building blocks to maximize the speed of operation and to minimize the power consumption.
The chip was implemented in a 90nm digital CMOS technology. Measurements on silicon show a power consumption of only 69µW at a sampling rate of 10Msamples/s and a standby power of only 17nW. Since none of the ADC building blocks consumes any static power, the power consumption of the ADC scales linearly with the sampling frequency. Thus, the figure of merit of 30fJ/conversion step is maintained from 10kSamples/s to 10MSamples/s making it the widest power-efficient range published amongst comparable state-of-the-art designs.
“This result proves that imec and Holst Centre have built up extensive know-how in ultra-low power design within their program on ultra-low power radios for body-area networks. This extreme low-power ADC is applicable in ultra-low power radios usable in a wide range of applications from healthcare to industrial;” said Bert Gyselinckx, general manager imec the Netherlands at Holst Centre.