Fin-shaped flash memory cells for use in MCUs

7th December 2016
Source: Renesas
Posted By : Alice Matthews
 Fin-shaped flash memory cells for use in MCUs

The successful development of Renesas Electronics' Split-Gate Metal-Oxide Nitride Oxide Silicon (SG-MONOS) flash memory cells has been announced, employing transistors with fin-shape for use in microcontrollers (MCUs) with on-chip flash memory having a circuit linewidth of 16 to 14nm or finer. SG-MONOS technology is reliable for use in automotive applications.

Renesas currently mass produces 40nm MCUs using this technology, and 28nm MCUs are under development. The successful development shows scalability of the SG-MONOS technology to 16/14nm process nodes and beyond.

Advances in automotive automation, such as Advanced Driver Assistance Systems (ADAS), and the smart society connected via the Internet of Things (IoT) have created demand for more advanced MCUs fabricated using finer process technology. To address this demand, Renesas has developed embedded flash memories based on the 16/14nm technology, which succeeds the 40/28nm. At the 16/14nm logic process, Fin Field Effect Transistors (FinFETs), transistors with a finned structure, are commonly employed to realise improved performance and reduced power consumption to overcome the scaling limit of conventional planar transistors.

However, employing a fin structure for embedded flash memory can become a big challenge depending on the structure of the flash memory. Two types of embedded flash memories have been proposed and implemented: the floating-gate and charge trap. Compared with floating-gate memory, the charge trap flash memory which Renesas has been utilising in recent years has superior charge retention characteristics and a proven track record in automotive MCUs requiring a high level of reliability. Also, since the memory functional material is formed on the surface of the silicon substrate, they are comparatively easy to be extended into a three-dimensional fin structure. In contrast, floating-gate flash memory cells have a complex structure, and therefore it is difficult to integrate it into a fin structure.

Another advantage of SG-MONOS over the floating-gate structure is that the memory cell structure is maintained after replacing the dummy polysilicon gate electrode with the metal gate electrode, which is the process used to manufacture advanced logic CMOS devices with high dielectric gate insulators and metal gate electrodes.

According to Renesas, it is the world’s first company to successfully develop a fin-structure SG-MONOS flash memory with highly scalability, for use in high-performance and highly reliable MCUs of 16/14nm process nodes and beyond.

Key features of the newly developed embedded flash memory technology:

  1. Confirmed improvement in memory operation and transistor characteristics due to fin structure
    Renesas has confirmed that the change in the threshold voltage during programming/erasing and the programming/erasing speed of the newly developed fin-structure SG-MONOS memory cells are within the anticipated ranges. In transistors employing a fin structure the gate encloses the channel, thereby a large drive current can be maintained, even when the footprint of the active area is substantially reduced to increase integration. In addition, a notable improvement in threshold voltage variability has been achieved by the enhanced gate controllability. These results indicate that fin-structure SG-MONOS memory cells have promising characteristics contributes to the realisation of the high-speed random access reads at frequencies at more than 200MHz required of next-gen flash memory, as well as drastic increases in on-chip memory capacity.
  2. Development of programming method that mitigates performance degradation due to fin structure
    When a fin structure is used, there may be some degradation or deterioration over time in device characteristics due to electric field enhancements at the tips of the fins. This electric field enhancements are most notable at the start of and immediately after programming operations, so Renesas engineers studied the feasibility of a 'step pulse' programming method in which the programming voltage is raised stepwise from a lower to a higher level. This is a technology that has already been announced as adopted for memory employing a planar structure, however in fin-structure memory it has proven to be particularly effective in mitigating electric field enhancements at the tips of the fins. Its effectiveness in actually reducing degradation over time in fin-structure SG-MONOS memory cells has been confirmed, and an program/erase cycle count of 250,000 has been achieved in flash memory for data storage.
  3. Maintenance of equivalent high-temperature data retention
    The fin structure matches the charge retention characteristics that are a feature of charge trap MONOS flash memory. Data retention duration, which becomes essential in automotive applications, is ten years or more after 250,000 programme/erase cycles. This is the same level of reliability found in earlier memory types.

The results described above indicate that SG-MONOS flash memory can easily be integrated with a fin-structure logic process utilising high dielectric gate insulators and metal gate electrodes at the 16/14nm nodes and beyond, enabling on-chip memory capacities in the 100MB range, and making possible reliable MCUs with over four times the processing performance of 28nm devices. Renesas will continue to confirm the operation of large-capacity flash memory based on this technology, and will move forward with development work with a view toward practical implementation around 2023.

Renesas intends to continue to engage in the development meant for high-performance, reliable large-capacity flash memory for embedded devices not only of the 28nm nodes, but of the 16/14nm nodes and beyond, as part of an ongoing commitment to contribute to advances in the automotive field and the realisation of a smart society.

Renesas will announce details of the newly developed embedded flash memory technology on 6th December at International Electron Device Meeting 2016 (IEDM 2016), which runs from 5th-7th December 2016 in San Francisco, US.


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