DRP-accelerated image processing with MPUs

28th August 2019
Source: Renesas
Posted By : Lanna Cooper

The Dynamically Reconfigurable Processor (DRP) is runtime-reconfigurable hardware that combines the flexibility and expansion capability of a software programmable CPU with the performance and efficiency of dedicated IP. 

Pairing a DRP with an Arm Cortex-A9 core and 4 MB of on-chip RAM, the Renesas RZ/A2M microprocessor enables a new, hybrid approach to image processing.

Designers can create machine vision applications that satisfy the size, power, and cost constraints of embedded systems, supported by a flexible methodology for the rapid time to market and iterative product feature enhancements required for competitive products.

For more information, watch the video below. 

You must be logged in to comment

Write a comment

No comments

Sign up to view our publications

Sign up

Sign up to view our downloads

Sign up

European Microwave Week 2019
29th September 2019
France Porte De Versailles Paris
HETT 2019
1st October 2019
United Kingdom EXCEL, London
World Summit AI 2019
9th October 2019
Netherlands Taets Park, Amsterdam
New Scientist Live 2019
10th October 2019
United Kingdom ExCeL, London
GIANT Health Event 2019
15th October 2019
United Kingdom Chelsea Football Club Stadium, London