What are the hardware latencies associated with PRU?
In this application report from Texas Instruments, the hardware latencies associated with PRU-initiated memory reads are explored. The PRU is a scalar processor, processing each instruction sequentially. With the exception of memory read instructions, all PRU instructions execute in a single cycle.
However, the execution time of PRU read instructions varies based on memory access latencies. Subsequent instructions will not execute until the completion of the read instruction and may impact time-sensitive operations and applications.
SoC Resources: To access SoC resources outside of the PRU Subsystem, the PRU accesses must go through external layer(s) of interconnects. In other words, the PRU must go through the local 32-bit Interconnect Bus and varying levels of L3/L4 interconnects external to the subsystem before reaching the resource.
This access path is much longer than the PRU's access path to local subsystem resources, causing longer access latencies. Additionally, the access latency for external resources will be indeterministic, as they varies based on system processing loads.
To read the report, click here.
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