Demand for NAND-based digital memory is booming, driven by increased use of devices that span the consumer and mobile markets, automotive and industrial sectors and the emerging Internet of Things (IoT). By Eugen Pfumfel, Principal Engineer, Memory Marketing, Toshiba Electronics Europe
Since Toshiba introduced NAND in 1984, the technology landscape and market has evolved significantly. NAND bit densities have increased more than 2000-fold due to the size of the process node dropping from 700nm to 15nm, and the introduction of new cell level technologies. Accompanying this increase in density has been a dramatic reduction in the price per Gb, which has decreased even faster than the bit density has increased – making NAND the storage medium of choice for many applications.
However, while the price per bit has decreased, moving to the latest technologies and process nodes is not always simple. One of the key challenges for those wanting to use the very latest raw NAND designs in their devices is that new NAND technologies tend to require more powerful error correction code (ECC) engines to be built into the controllers – and this has become an on-going race as, generally speaking, there is often a wait for the controllers to catch up.
For instance just 1 bit ECC per 512bytes is required for single level cell (SLC) NAND down to 43nm,. This increases to 8bits of ECC per 512bytes for 24nm SLC NAND, meaning the switch from 43nm Raw SLC NAND to 24nm Raw SLC NAND can cause a significant negative impact on performance unless more advanced controller technology is implemented.
Levelling the wear
While the technology exists to make NAND at even smaller process nodes, as the cells get smaller endurance and reliability start to come in to play. And further NAND cells that can store multiple bits have been developed – single level cell (SLC) NAND can store 1 bit per cell, multi-level cell (MLC) NAND can store 2 bits per cell, while triple level cell (TLC) NAND can store 3 bits per cell. However, write/erase endurance is affected by such approaches – SLC can endure around 60,000 cycles, MLC 3,000 cycles and TLC 500 cycles (assuming the same ECC algorithm).
Because NAND memory blocks can degrade and wear out, an upper limit is placed on the number of writes to each NAND memory location. ‘Wear levelling’ algorithms also need to be built into NAND controllers to ensure NAND memory locations are used evenly.
When calculating the system lifetime using NAND reliability, it’s important to remember that memory management functions cause more writes to each cell than just the number of bits of data that are originally written. This is because memory management functions can involve moving data from place to place resulting in multiple cell writes for each bit of data to be stored.
While write/program of NAND is conducted on a page-by-page basis, erase functions delete entire blocks (which consist of multiple pages). To prepare a block for erase, data to be retained is first copied into other blocks. This page shuffling before block erase is called garbage collection.
Reducing the burden on the controller
For many existing applications that use SLC NAND memory, such as industrial designs, communication processors and automotive systems, the 1-bit ECC is implemented in the host software with no significant effect on application performance. Migrating to ‘cutting-edge’ memories that require 4-, 8- or even 24-bit ECC significantly increases demand on the processor, reducing performance. In order to avoid this performance penalty, NAND chips with embedded ECC have become the preferred solution. Toshiba’s BENANDTM (Built-in ECC NAND) offers such a solution and removes the burden of ECC from the host processor without requiring an additional hardware controller.
BENAND uses the well-established, common NAND interface, ensuring compatibility with raw SLC NAND Flash in areas such as command set, device operation, packaging and pin configuration. The host system handles issues such as bad-block management, wear levelling, address mapping and garbage collection in the same way as with raw SLC NAND.
BENAND devices are available from 1Gb to 8Gb density, packaged as standard TSOP-I-48-P and 63-ball BGA devices that are pin compatible with known SLC packages. A tiny 6.5mm x 8.0mm 67-ball BGA version is also available, which enables designers to meet tight space constraints in new designs.
Direct pin and package compatibility between raw SLC NAND and BENAND allows straightforward drop-in replacement when upgrading to the latest-generation Flash. This approach has enabled Toshiba’s engineers help customers integrate BENAND into both existing and new designs, delivering the benefits of migrating to the latest device technology while avoiding the high costs associated with significant system redesign or long-term use of legacy technology.
Removing the need for a NAND controller
e.MMC NAND takes the migration of memory management functions one-step further than BENAND – it integrates the NAND flash memory and whole controller chip in a single package. These devices are compliant with JEDEC standards and are typically used in smartphones, tablets, set-top boxes, TVs and also in industrial computer modules. The embedded controllers perform operations such as error correction, wear levelling and bad-block management to ensure the NAND memory operates correctly.
e.MMC solutions are typically based on MLC NAND and combine raw MLC NAND with a NAND controller. To increase the reliability of the memory when the data is changed at high frequency, managed MLC can use a mode called pseudo-single level cell (pSLC), which emulates SLC NAND by storing just one bit in each MLC cell. This approach enables data to be changed ten times more frequently than standard MLC NAND operation, with comparable levels of reliability. This may be useful in applications such as in set-top boxes that can pause live TV, where data is very frequently overwritten. pSLC mode needs to be activated during first initialisation and the NAND controller manages the MLC memory as normal.
High capacity e.MMC can make use of techniques such as interleaving, in which performance can be increased by addressing multiple regions in parallel. During write and erase operations, the NAND memory bus is in busy mode and must wait for a reply. If the integrated NAND controller can access another NAND die or separate NAND register/bus, multiple access (read, write and erase) is possible.
The interface for e.MMC products is specified by an industry body called JEDEC, and it’s standardised to ensure interoperability between different manufacturers’ products. The e.MMC card interface is standardised on a 8/4/1 bit parallel data-bus plus a few control signals. In contrast, Raw NAND interfaces are not necessarily standardised and use an 8bit parallel data-bus plus many more control pins.
The latest version of the JEDEC standard, e.MMC v5.0, defines a higher speed interface (HS400) to meet the needs of high performance systems. It also includes update procedure that allows installation of a new version of the e.MMC device controller firmware once the product is in the field. A sleep notification function allows a safer transition to lower power sleep modes.
A key feature of any version is backwards compatibility with e.MMC products that comply with earlier versions of the standard. For that reason, while it’s possible to get better performance from newer v5.0 pin layouts, the new layout is also backward compatible.
As with all digital ICs, there is a trend toward increased performance and lower power consumption in denser packages; and Toshiba uses its 15nm process node for its e.MMC flash to meet these needs. There is also a need to ensure the lifetimes of older products can be extended, and BENAND is answering those needs by enabling engineers to specify the latest NAND technologies without having to upgrade controller hardware.
There is also trend towards widening operating temperature ranges for e.MMC NAND flash products. Standard operating temperature range for e.MMC for consumer electronics products is -25 to +85°C. Toshiba has started producing devices that are suitable for industrial and automotive infotainment applications with an operational temperature range between -40 and +85°.
Looking a little bit further into the future, super-high-end smartphones and tablets will be the first to move on from the current format of e.MMC. The technology has evolved into a new format called universal flash storage (UFS), which is currently in the early stages of volume production. With initial data throughput of 300MB/s (2.9Gbps single lane) the devices are aimed at the high end of the consumer electronics sector. Next generation specifications achieve lane speeds of 5.8/11.6Gbps and can be implemented as multi-lane solutions. Data can be transferred over its serial bus in both uplink and downlink directions simultaneously.
Designers of smart devices are demanding smarter, faster and higher capacity NAND devices that enable backwards compatibility and easier implementation. With extensive experience of developing both its own NAND and controller technologies, Toshiba designs both in tandem to offer reliable, and performance-optimised memory solutions for today’s, tomorrow’s and even yesterday’s devices.