volatile Flash memory for code and data storage is now an essential element in a growing variety of electronic systems and products ranging from industrial control equipment through home and office networking and automation hardware, to consumer devices and automotive electronics. And as the need to manage ever-greater data volumes and to deliver ever-improved functionality and performance grows — along with the requirement for reliability — so too does the pressure on designers to select the optimum Flash solution.
Today’s embedded engineers have a vast array of discrete memory products and technologies from which to choose. Historically, the choice for Flash memory may simply have been between NOR and NAND. NOR Flash, while physically larger, would typically be used for code storage, while the very low cost-per-bit and small chip size of NAND Flash making it the primary choice for high-density storage. However, significant developments in the NAND arena have made it a viable option for both expanding software protocols (code) and data, not least in designs requiring high programming and erase speeds and high-efficiency, low-power operation.
So what are the criteria for NAND Flash selection? Firstly, a consideration of the type of NAND Flash technology deployed in a particular component is worthwhile. This typically means multi-level cell or single-level cell. Thanks to its ability to store two (or more) bits per cell, MLC has obvious advantages in terms of storage per area. SLC, on the other hand, stores a single bit per cell but can typically deliver faster read / write speeds and higher reliability. In general, SLC is the preferred solution for boot and application software and for meeting rigorous requirements for robustness and long-life design (in the region of 60,000 to 100,000 erase/program cycles or more). For applications where density is of primary importance then MLC, which typically offers erase/program cycles in the area of 10,000, may offer the best approach.
In either case as storage capacities increase to accommodate new demands then so must silicon areas, which, in turn, leads to increased costs for a given process geometry. Shrinking the process geometry, however, can deliver smaller silicon areas and, thus, reduce costs. As a result, there is often significant pressure on designers to use the latest process geometries.
But the underlying technology is only one part of the story. Another important aspect of design is implementation of error correction code or ECC. ECC is necessary in the vast majority of NAND Flash designs to identify and correct incorrect data bit values (from the remaining good values) that can occur thanks to environmental factors or ‘wear and tear’. To date, for example, most manufacturers have required more error correction bits for MLC technologies. However, only 1-bit ECC has been needed for SLC – at least in the case of densities up to 4Gb fabricated using a 43nm semiconductor process.
This situation is now changing thanks to advances in the underlying memory process technology. Specifically, enhanced error correction is required if new and emerging NAND Flash memories are to guarantee the 60,000 or more erase/program cycles that engineers expect. For SLC NAND Flash fabricated in a 32nm / 24nm process, for instance, more than 4-bit / 8-bit per 512 bytes ECC is now required.
The choice for the designer is whether to implement ECC in software or through an additional hardware controller. For many existing applications that use SLC NAND memory, for example — including industrial designs, communication processors and automotive systems — the choice has been made to implement the relatively low overhead of the 1-bit ECC in the host software. Migrating to 4- or 8-bit ECC puts a significantly greater demand on the processor, often requiring so much processing power that it becomes unviable for a software implementation to handle the new level of error correction. This means that beyond the 1-bit level designs have required the implementation of new hardware NAND controllers to take advantage of new ‘cutting edge’ memory.
BENAND and Raw SLC NAND
Built-in ECC and SLC NAND
Recently, in the case of the latest SLC NAND solutions, a new option has become available to the designer, namely BENAND memory, which features an embedded ECC function. As figure 1 illustrates, BENAND removes the burden of ECC from the host processor (or eliminates the need for an additional hardware controller) while use of the common NAND interface ensures compatibility with general SLC NAND Flash in areas such as command set, device operation, packaging and pin configuration. The result is a technology that allows OEMs to benefit from the cost and space reductions associated with smaller process geometries — whether in completely new designs or migrating existing applications to more advanced memory solutions.
BENAND devices in 4Gbit and 8Gbit capacities and featuring integrated 4-bit per 512 bytes ECC and 32nm process NAND flash memory are already available in various package formats. Page size for these devices is 4Kbyte. Shortly the range of devices will be further expanded with both new 1Gbit and 2Gbit options fabricated using the latest 24nm process technologies becoming available.
MLC Options with Integrated ECC
For applications where the features of MLC NAND Flash memory are more attractive there are also device options that provide integrated ECC functionality and, therefore, simplify and speed design and development.
Toshiba’s next-generation SmartNAND, for example, integrates leading-edge 24nm process NAND Flash technology with a control chip that supports ECC. Available in densities ranging from 4Gbyte to 64Gbyte and working with page sizes of 8Kbyte, SmartNAND again removes the burden of ECC from a host processor while minimising protocol changes. Target applications include portable media players, tablet PCs, digital televisions, set-top boxes and other devices requiring high-density, non-volatile memory. By enabling the system designer to directly manage the NAND with host controller, SmartNAND results in faster time-to-market, access to leading geometries and potentially lower design costs when compared to conventional NAND flash implementations that require external ECC. There is a further advantage; commonly the availability of external or integrated (within the host system) NAND controllers is not synchronised with availability of the raw MLC memory. By definition SmartNAND always has an ECC controller that is optimised for the MLC implementation simplifying NAND management through host software.
Furthermore, SmartNAND offers a range of read and write speeds (to provide designers with a selection that is best-matched to a given application) and a choice of ‘normal’ and ‘reliable’ modes. The former delivers standard, 2-bit-per-cell operation and the latter provides ‘pseudo-SLC’ operation.
A third category of NAND Flash technology that is gaining prominence is e•MMC-compliant memory. This time the devices offer an interface that complies with the JEDEC e•MMC embedded multimedia card standard and combine multiple MLC NAND chips with a dedicated controller in a single, compact package. The controller performs all necessary error correction, wear levelling and bad block management, significantly simplifying application design and development. Toshiba’s line-up of e•MMC devices offers densities ranging from 2Gbyte to 128Gbyte fabricated on a 24nm semiconductor process.
NAND Flash Memory with Built-in ECC
Figure 2 shows how the various SLC and MLC NAND Flash technologies with integrated ECC options compare to each other as well as to ‘pure’ NAND Flash memory.
Naturally consideration of embedded memory solutions will always need to take into account a variety of factors: read and write speed, package format, capacity, size and anticipated lifetime being among the most obvious. What is clear is that there is no shortage of choice for today’s designer and that, increasingly, this choice is available with on-board ECC and other key functions required for effective NAND Flash deployment. As a result designers can not only reduce development overhead and drive down project cost, but can also quickly and easily migrate existing applications to take advantage of new and emerging memory technologies.
Author profile: Eugen Pfumfel is a Principal Engineer with Toshiba Electronics Europe.