Manufacturability of spin-orbit torque MRAM devices demonstrated at Symposia

19th June 2018
Source: IMEC
Posted By : Alex Lynn
Manufacturability of spin-orbit torque MRAM devices demonstrated at Symposia

At the 2018 Symposia on VLSI Technology and Circuits, Imec demonstrated the possibility to fabricate spin-orbit torque MRAM (SOT-MRAM) devices on 300mm wafers using CMOS compatible processes. 

With an unlimited endurance (>5x1010), fast switching speed (210ps), and power consumption as low as 300pJ, the SOT-MRAM devices manufactured in a 300mm line achieve the same or better performance as lab devices. This next-gen MRAM technology targets replacement of L1/L2 SRAM cache memories in high-performance computing applications.

SOT-MRAM has recently emerged as a non-volatile memory technology that promises a high endurance and low-power, sub-ns switching speed. With these properties, it can potentially overcome the limitations of spin-transfer torque MRAM (STT-MRAM) for L1/L2 SRAM cache memory replacement. SOT-MRAM devices had only been demonstrated in the lab, but Imec has now proven full-scale integration of SOT-MRAM device modules on 300mm wafers using CMOS-compatible processes.

At the core of the SOT-MRAM device is a magnetic tunnel junction in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. Similar as for STT-MRAM operation, writing of the memory is performed by switching the magnetisation of this free magnetic layer, by means of a current. In an SOT-MRAM device, switching of the free magnetic layer is done by injecting an in-plane current in an adjacent SOT layer, typically made of a heavy metal. Because of the current injection geometry, the read and write path are de-coupled, significantly improving the device endurance and read stability.

Imec has compared SOT and STT switching behaviour on one and the same device, fabricated on 300mm wafers, reliable switching down to 210ps was demonstrated during SOT-MRAM operation. The SOT-MRAM devices show endurance (>5x1010) and operation power as low as 300pJ. In these devices, the magnetic tunnel junction consists of a SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetised stack, using beta-phase tungsten (W) for the SOT layer.

Gouri Sankar Kar, Distinguished Member of Technical Staff at Imec, stated: “STT-MRAM technology has a high potential to replace L3 cache memory in high-performance computing applications. However, due to the challenging reliability and increased energy at sub-ns switching speeds, they are unsuitable to replace the faster L1/L2 SRAM cache memories. SOT-MRAM technology will help us to expand MRAM operation into the SRAM application domain. By moving this next-generation MRAM technology out of the lab, we have now demonstrated the maturity of the technology.”

Future work will aim to focus on further reducing the energy consumption, by bringing down current density and by demonstrating field-free switching operation.


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