Low power SRAM customises memory for artificial intelligence

21st March 2019
Posted By : Lanna Cooper
Low power SRAM customises memory for artificial intelligence

 

sureCore's new SureFit SRAM customisation service has delivered low power high capacity SRAM subsystems implemented in advanced FinFET processes to Tier-1 players in the demanding imaging, artificial intelligence and machine learning markets.

The SureFit developed memory system integrates very large memory arrays, delivering high bandwidth, low latency and multi-port capabilities required by these data intensive applications.

It builds on sureCore's patented power saving technology that provides both functional and power optimised memories to deliver unprecedented dynamic and static power savings for multi-megabyte, on-chip SRAM arrays.

"SureFit memories deliver power efficiencies by coupling custom innovative low power single port memories tiled in an array with energy efficient interconnect and intelligent memory subsystem control. The result is pseudo multi-port operation with minimum area, dynamic power and leakage," said Paul Wells, CEO.

By engaging with leaders across a broad range of markets, sureCore has developed bespoke solutions tailored to meet precise application demands that have delivered up to 70% power savings.

"AI/ML investments exceeded $19bn in 2018. A key facet of these applications is the integration of large multi-port SRAMs. For many edge devices, off-the-shelf solutions don't deliver the necessary power efficiencies. Current customer engagements are a testimony to SureFit's ability to provide custom, optimised memory solutions tailored to precise specifications," Wells said.

Delivering competitive and differentiated power efficient solutions means addressing the memory subsystem design. Adopting a bottom-up custom design strategy enables closer alignment with the system architecture resulting in a more power and feature-optimised solution.

Laying out a roadmap for future developments Wells commented that: "We are actively exploring integrating computational elements within the memory subsystem to further increase processing capacities and cut power budgets."

Delivering competitive products in this space necessitates a holistic approach to system level considerations. As Wells puts it: "Low power SRAM is no longer just low power SRAM!"


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