Differential DIMM at Flash Memory Summit

7th August 2019
Posted By : Alex Lynn
Differential DIMM at Flash Memory Summit

SMART Modular Technologies has announced that it is showcasing its Open Memory Interface (OMI) DDR4 Differential DIMM (DDIMM) at this week’s 2019 Flash Memory Summit in Santa Clara, California. SMART Modular joined a growing roster of technology organisations (in August) contributing to the OpenCAPI Consortium, working collaboratively to drive data centre server innovation.

Through the Consortium, members are working to innovate on top of OpenCAPI, a high performance coherent bus standard designed to help the technology industry better meet the growing demands for more advanced memory, accelerators, networking and storage technology.

Using the OMI specification, developers can enable high performance accelerators like FPGAs, GPUs, and network and storage accelerators to perform functions that a server’s general purpose CPU is not optimised to execute.

SMART’s OMI DDR4 DDIMM is a leading-edge, transformative memory module that enables a data throughput rate of 25.6GB/s with a latency of 40ns and densities up to 256GB. The new 84-pin DDR4 DDIMM is intended for use in standard server environments, utilising a serial interface and a differential Data Buffer (dDB) from Microchip.

The DDIMM supports IBM’s P9 AIO and P10 processors’ memory attached architecture. The P9 AIO and P10 memory bus is defined with one read port and one write port per channel, each having eight unidirectional differential lanes supporting 25.6 Gbps data rate over the OMI direct attached to the DDIMM.

Andrew Dieckmann, Vice President of Marketing and Applications of the Data Center Solutions business unit at Microchip’s Microsemi subsidiary, said: “Microchip’s SMC 1000 8x25G is the industry’s first Open Memory Interface (OMI)-to-DDR4 DRAM serial memory controller and a key building block for the SMART Modular OMI DDIMM.”

“CPU- and compute-centric SoC devices can achieve four times the memory bandwidth per pin, memory media type independence, and lower system memory costs by adopting technologies such as OMI-based DDIMMs over traditional parallel DDR DIMMs.”

The development model of the OpenCAPI Consortium is one that elicits collaboration and represents a new way in exploiting and innovating around coherent accelerator processor technology. SMART has made significant contributions to the development and production of the DDR4 DDIMM to further advance differentiation and growth of the OpenCAPI ecosystem.

The 2019 Flash Memory Summit will be held August 6th to 8th at the Santa Clara Convention Center.

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