Industries

ACM Research receives contract for plating systems

10th May 2022
Louis Regnier

10 ECP ap tools purchased by top-tier Chinese OSAT to support wafer-level packaging applications

ACM Research, a supplier of wafer processing solutions for semiconductor and advanced wafer-level packaging applications, have announced that a volume purchase contract has been received from a Chinese OSAT for 10 Ultra ECP ap high-speed plating tools, which are scheduled to be delivered later in 2022 and 2023. The Ultra ECP ap system with new high-speed plating technology has been previously qualified by multiple OSAT customers for advanced WLP applications. The new purchase orders, which build on orders announced in February 2022 for 21 ECP tools from a top-tier Chinese foundry and multiple advanced packaging houses, demonstrate the increased market traction for ACM’s ECP technologies for both advanced packaging and front-end customers.

“A wide range of applications, such as 5G cellular phones and autonomous vehicles, are increasingly demanding high-performance microprocessors to meet emerging demands for novel WLP structures,” said Dr. David Wang, ACM’s President and Chief Executive Officer. “This is driving strong demand for our ECP ap high-speed plating systems, with proven performance that has resulted in multiple orders this calendar year. This new contract for 10 tools from a leading Chinese OSAT demonstrates customer confidence and satisfaction in our high-speed plating technology and further increases our share in this rapidly growing advanced packaging market.”

ACM’s Ultra ECP ap plating tool supports copper (Cu) pillar bumping for Cu, nickel (Ni) and tin-silver (SnAg) plating, as well as high-density fan-out (HDFO) WLP product with warpage wafers for Cu, Ni, SnAg and gold plating. Its high-speed plating technology with proprietary paddle design provides stronger mass transfer during the plating process, coating all pillars on the entire wafer concurrently at the same plating rate. This provides improved uniformity below 3% within wafer and within die during high-speed plating. It also offers better coplanarity performance and higher throughput. The single-wafer, flat-type plating design eliminates cross-contamination between chemical baths in vertical-type plating design.

 

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