Intel ships first 10nm Agilex FPGAs

2nd September 2019
Source: Intel
Posted By : Alex Lynn
Intel ships first 10nm Agilex FPGAs

Intel today announced that it has begun shipments of the first Intel Agilex field programmable gate arrays (FPGAs) to early access program customers. Participants in the early access program include Colorado Engineering, Inc., Mantaro Networks, Microsoft and Silicom. These customers are using Agilex FPGAs to develop advanced solutions for networking, 5G and accelerated data analytics.

Dan McNamara, Intel senior vice president and general manager of the Networking and Custom Logic Group, said: “The Intel Agilex FPGA product family leverages the breadth of Intel innovation and technology leadership, including architecture, packaging, process technology, developer tools and a fast path to power reduction with eASIC technology.

“These unmatched assets enable new levels of heterogeneous computing, system integration and processor connectivity and will be the first 10nm FPGA to provide cache-coherent and low latency connectivity to Intel Xeon processors with the upcoming Compute Express Link.”

In the data-centric, 5G-fuelled era, networking throughput must increase, and latencies must decrease. Intel Agilex FPGAs provide the flexibility and agility required to meet these challenges by delivering significant gains in performance and inherent low latency. 

Reconfigurable and with reduced power consumption, Intel Agilex FPGAs have computation and high-speed interfacing capabilities that enable the creation of smarter, higher bandwidth networks and help deliver real-time, actionable insights via accelerated artificial intelligence (AI) and other analytics performed at the edge, in the cloud and throughout the network. 

Doug Burger, technical fellow, Azure Hardware Systems at Microsoft, added: “Microsoft has been working closely with Intel on the development of their Intel Agilex FPGAs and we are planning to use them in a number of upcoming projects. 

“Intel FPGAs have provided tremendous value for us for accelerating real-time AI, networking, and other applications/infrastructure across Azure Cloud Services, Bing, and other data centre services. We look forward to continued collaboration with Intel to deliver high quality cloud services, big data analytics, and ultra-intelligent web search results for our customers.”

The Intel Agilex family combines several innovative Intel technologies including the second-generation HyperFlex FPGA fabric built on Intel’s 10nm process, and heterogeneous 3D silicon-in-package (SiP) technology based on Intel’s proven embedded multi-die interconnect bridge (EMIB) technology. This combination of advanced technologies allows Intel to integrate analog, memory, custom computing, custom I/O and Intel eASIC device tiles into a single package along with the FPGA fabric. Intel delivers a custom logic continuum that allows developers to seamlessly migrate their designs from FPGAs to structured ASICs. 

Intel Agilex FPGAs provide innovative new capabilities to help accelerate the solutions of tomorrow. Innovations include:

  • Compute Express Link: Industry’s first FPGA to support upcoming Compute Express Link (CXL), a cache and memory coherent interconnect to future Intel Xeon Scalable processors.
  • 2nd-generation HyperFlex architecture: Up to 40% higher performance or up to 40% lower total power2 compared with Intel Stratix 10 FPGAs1.
  • DSP innovation: Only FPGA supporting hardened BFLOAT16, with up to 40 teraflops of digital signal processor (DSP) performance (FP16).
  • Peripheral component interconnect express (PCIe) Gen 5: The ability to scale for higher bandwidth compared with PCIe Gen 4.
  • Transceiver data rates: Support up to 112 Gbps data rates for high-speed networking requirements for 400GE and beyond.
  • Advanced memory: Support for current DDR4, and upcoming DDR5, HBM, and Intel Optane DC persistent memory.

Design development for Intel Agilex FPGAs is available today via Intel Quartus Prime Design Software, which delivers the highest performance and productivity for Intel FPGA, CPLD, and SoCs.


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