FPGAs

Lattice Semiconductor and Praesum Communications today announced the availability of the Serial RapidIO 2.1 endpoint soft IP core for the LatticeECP3 FPGA family. The core supports 1x, 2x and 4x lane configurations at up to 3.125Gbps lane speeds, offering the lowest cost, lowest power programmable SRIO solution in the industry. Lattice also announced that it has licensed this IP core from Praesum and has full rights to use and sub-license the Serial RapidIO IP core.

Lattice Semiconductor today announced that the LatticeECP3-150 FPGA, the highest-density device in its award-winning high-value, low-power ECP3 mid-range FPGA family, has been fully qualified and released to volume production.

Xilinx, Inc. today announced the availability of the industry's first IBIS-AMI models for FPGA transceivers. Xilinx is the first FPGA provider and among the first silicon vendors to release IBIS-AMI models for its transceiver technology that will enable designers to reduce simulation time from hours to minutes. Xilinx and Signal Integrity Software, Inc. (SiSoft) will hold a free webinar on Thursday, Nov. 12 to outline the advantages of using IBIS-AMI models for transceiver simulation.

At IBC2009, Xilinx, Inc. announced the integration of Xilinx field programmable gate arrays in the latest digital TV and mobile TV modules from TeamCast, a world leader in mobile TV and DTV transmission technology innovations. TeamCast credits the full range of high capacity and cost-effective Xilinx device options, combined with the ability to embed processing and programmable logic in a single FPGA, as key factors in providing the flexibility and price-performance required to succeed in the professional broadcast market.

Lattice Semiconductor Corporation today announced that samples of the LatticeECP3-150 FPGA, the highest-density device in its high-value, low-power ECP3 mid-range FPGA family, are now generally available. Samples have already been shipping to select customers since July of this year.

Altera has announced it has started shipping Arria II GX devices, its third family of 40-nm FPGAs. The Arria II GX family with integrated transceivers joins Stratix IV GX and Stratix IV GT FPGAs and HardCopyIV GX ASICs to extend the industry' broadest portfolio of transceiver FPGA and ASIC solutions.

Altera has announced silicon availability of the industry’s highest density transceiver FPGA. As the second member of the Altera Stratix IV GX FPGA family to ship, the EP4SGX530 is 60 percent larger than the largest transceiver FPGA on the market. The device offers 530K logic elements (LEs), up to 48 transceivers operating at up to 8.5 Gbps, 20.3 Mbits of RAM and 1,040 embedded multipliers. Stratix IV GX devices target numerous applications in the communications, broadcast, test, medical and military markets.

The recent addition of high-speed UARTs to the library of functions for QuickLogic's low-power, configurable Customer Specific Standard Product (CSSP) logic platforms for consumer electronics, is providing a versatile upgrade path for smartphone developers. It offers a power-efficient single-chip solution to expand the interfacing capability of a mobile application processor to support high-datarate Bluetooth, as well as the integration of further high-desirability peripherals such as GPS.

CISSOID has announced its CHT-74 Logic Family for extreme temperatures. The products are optimized for High-Temperature, High Reliability applications. They bring digital functions to system designers targeting high temperature electronics, even beyond 200°C.

Linear Technology has expanded its I2C and SMBus Bus Buffer and Rise Time Accelerator family with the introduction of the LTC4308 and LTC4309. As the number of plug-in boards continues to increase, additive capacitances begin to critically lengthen rise times. Breaking the bus into several pieces with bus buffers alleviates this problem, but if the buffer offsets are too large, logic low voltage specifications may be violated.