New process improvements for next-gen devices were unveiled by imec at 2017 Symposia on VLSI Technology and Circuits. For the first time, scaled strained germanium p-channel Gate-All-Around (GAA) FETs were shown with sub-10nm diameter, integrated on a 300mm platform. In addition, the research centre has obtained a significant improvement in device performance and electrostatic control with high-pressure anneal (HPA) for both strained germanium p-channel FinFET and GAA devices.
High-mobility materials such as germanium and III-V have been considered as potential solutions for deeply scaled devices, due to their higher intrinsic carrier mobility. However, these materials have a larger permittivity and a smaller bandgap than silicon, making it more difficult to apply the necessary electrostatic control at scaled gate lengths. To mitigate this issue, new device architectures with better electrostatics are necessary. Imec’s results bring significant improvements for both strained germanium p-channel FinFET and gate all around (GAA) devices.
Nadine Collaert, Distinguished Member of Technical Staff at imec, said that her team “adapted the process flow of our previously published 14/16nm-node strained germanium p-finFETs to study the benefit of strained germanium GAA p-FETs at short gate lengths and sub-10nm diameter.” The team managed to process GAA p-FETs with the shortest gate lengths (LG=40nm) and smallest nanowire diameter (d=9nm) reported to date. At these shortest gate lengths, the devices maintain excellent electrostatic control with a drain-induced barrier lowering of 30mV/V and a sub-threshold slope of 79mV/dec.
In a second paper, imec reports on the use of high-pressure anneal (HPA) as a new performance booster for both germanium FinFETs and GAA devices. In their test, the researchers measured an improved interface quality and hole mobility (~600 cm2/Vs) as a result of a HPA at 450°C. The optimised HPA is also shown to significantly improve the electrostatics and overall performance of GAA devices, reaching SSLIN of 65mV/dec at LG=60 nm and a Q factor of 15 with a low IOFF of ~3×10-9A/μm.
Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programmes including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.