Record low source/drain contact resistivity for PMOS transistors

8th June 2017
Source: IMEC
Posted By : Alice Matthews
Record low source/drain contact resistivity for PMOS transistors

At this week’s 2017 Symposia on VLSI Technology and Circuits taking place in Japan, imec, the research and innovation hub in nano-electronics and digital technology, reported record breaking values below 10-9Ω/cm2 for PMOS source/drain contact resistivity. These results were obtained through shallow Gallium implantation on p-SiliconGermanium (p-SiGe) source/drain contacts with subsequent pulsed nanosecond laser anneal.

In future N7/N5 nodes, the source/drain contact area of the transistors becomes so small that the contact resistance threatens to become the dominating parasitic factor, resulting in suboptimal transistor functioning. Researchers have therefore been working on techniques to reduce the contact resistance on highly doped n-Si and p-SiGe source/drain contacts, aiming for values below 10-9Ω/cm2 . Together with colleagues from the KU Leuven (Belgium), Fudan University (Shanghai, China), and Applied Materials (Sunnyvale, USA), imec’s specialists concentrated on p-SiGe contacts, comparing the effects of high-dose Boron and Gallium doping.

For the comparison, the researchers implanted SiGe separate wafers with a high dose of Gallium or Boron and applied various anneal processes. They then fabricated multi-ring circular transmission line model structures, which are highly sensitive to contact resistance. Subsequent measurements revealed the lowest contact resistance for the Gallium-implanted structures annealed with Applied Material’s nanosecond laser anneal. This process causes a Ge/Ga surface segregation, which is responsible for the ultralow sub-10-9Ω/cm2 contact resistivity. This result show a possible way to process next-gen technology nodes.

Naoto Horiguchi, distinguished Member of the technical staff at imec indicated: “This breakthrough achievement in our search to develop solutions for next generation deeply-scaled CMOS provides a possible path for further performance improvement using the current source/drain schemes in N7/N5 nodes.”

imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programmes including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.


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