bps IP (Internet Protocol) -based asset delivery is going to be vital in the emerging multiplatform world where multiple video and metadata streams for various devices are moved around broadcast and operator networks, according to Tom Morrod, head of TV Technology for IHS Screen Digest. Programmable solutions are becoming increasingly important in dealing with flexible hardware-based video processes as we predict the increase in 3D and full 1080p60 HD content will need much higher bandwidth interfacing along with multiple transcodes in order to reach the expanding number of video-receiving devices.
The Real-Time Video Engine Targeted Design Platform consists of a broadcast-quality Video and Image Processing IP pack, as well as reference designs supporting the Virtex-6 FPGA and Spartan-6 FPGA Broadcast Connectivity Kits, which include Xilinx(R) ISE(R) Design Suite embedded development software. The combination of IP cores, tools and hardware makes it easier than ever before for designers to develop a real-time video processing chain for many types of broadcast applications that support various SD/HD/3D formats, frame rates and resolutions. The kits' FMC (FPGA mezzanine card) connectors allow designers to quickly evaluate and integrate SD/HD/3G-SDI, AES3 audio, DVI, HDMI(TM), DisplayPort, 10GbE (10 Gigabit Ethernet) for video over IP, and other interfaces into broadcast designs needing real-time performance, such as for breaking news, live events and sports coverage. Applications needing the highest video quality and highest bandwidth in digital cinema and Super Hi-Vision (or Ultra HDTV) systems can also be built.
Xilinx is demonstrating several key elements of its Broadcast Real-Time Video Engine Targeted Design Platform in Booth #N3722 at NAB 2011 including:
Xilinx's Video and Image Processing IP pack supporting 1080p60, 2K and 4K video processing, providing the capability to do scaling, deinterlacing, on-screen display, noise reduction and more at broadcast quality;
Implementation of the SMPTE2022 IP core showing full bandwidth, low-jitter 3x 3G-SDI (or 6x HD-SDI) over 10Gb Ethernet in full duplex running on the Virtex-6 FPGA Broadcast Connectivity Kit. This enables the delivery of up to six HD camera feeds uncompressed over a single link over virtually any distance;
The Inrevium Spartan-6 FPGA Broadcast Connectivity Kit from Tokyo Electron Devices supporting brand new low cost FMCs for SD/HD/3G-SDI and AES3 audio and optional FMCs for various display interfaces like HDMI, DisplayPort, and V-by-One(R) HS;
Virtex-7 HT FPGA 28 Gbps solution highlighting the excellent jitter performance of Xilinx's next generation transceivers and supporting huge amounts of aggregate bandwidth for communications and broadcast backhaul links, such as for EdgeQAM / CMTS applications in cable, also perfect for supporting the 10G-SDI standard and emerging standards to handle 4Kx2K digital cinema and Super Hi-Vision 8Kx4K bandwidths;
Xilinx Alliance Member Vanguard Software Solutions' H.264/AVC-I Video Encoder implementation showing how designers can reduce bandwidth and storage requirements without sacrificing video quality. Designers can quickly and easily integrate the AllianceCORE(TM) IP core into contribution, acquisition and archival systems and support SMPTE AVC-IClass50 & Class100, with High10 and High422 intra profiles.
Brand new Kintex(TM)-7 family, the industry's first 28nm FPGA is ideally suited for broadcast applications with transceivers capable of supporting up to 12.5 Gbps and offering 2x the performance at less than 50 percent the power of previous generation FPGAs.
Meeting the Fast Ramp-up to Higher Transmission Quality and Throughput
Broadcasters have multiple pain points in a continuously morphing environment featuring rapid growth in consumption of content and over more types of delivery networks, particularly over IP, while facing increasing pressure to keep video quality as high as possible, said Robert Green, senior manager, Broadcast Business at Xilinx. These new IP cores and reference designs further enhance the benefits customers were already enjoying by using FPGAs to get products quicker to market while easing their development effort.
The growing adoption of 3DTV will double the bandwidth requirements as compared to 1080p60 formats, subsequently increasing the number of SDI ports required in each system implementation or increasing the speed of these ports to 6 Gbps and upwards. The Xilinx Broadcast Real-Time Video Engine Targeted Design Platform accommodates today's triple-rate SDI- (SD/HD/3G-SDI) applications and accommodate the higher speeds required for Super Hi-Vision. Proposed standards such as dual 3G-SDI over 6 Gbps fiber, 10G-SDI as well as others on the industry roadmap, can also be supported.
Top-tier systems developers use FPGAs for both video algorithm development as well as transporting multiple channels of HD video across IP networks in either LAN (within the studio or stadium) or WAN (between cities and from stadium to studio) environments. FPGA-based implementations of integrating systems and processing on a single chip are superior to hard-cast silicon solutions such as ASICs or ASSPs because they require shorter development time while enabling developers to continually improve video quality. FPGAs also make bridging between ever-changing standards in both the broadcast and communications industries easier while providing high reliability quality-of-service transport of video over networks, and enabling the transport of the highest quality video over multiple streams.
Xilinx's extremely powerful FPGA technology facilitates the functionality we need with very high levels of integration and competitive pricing, said Andrew Osmond, Nevion USA vice president of Engineering. By using Virtex FPGAs, boards, IP cores and reference designs for implementing SMPTE2022 we were able to quickly develop and include this functionality in our Ventura product line to receive and transport compressed video over IP networks. This allows us to meet our customer's escalating bandwidth and processing demands.