Synopsys has announced availability of its Verification IP (VIP) and source code Test Suite for Arm AMBA ACE5 (AXI Coherency Extensions) and AXI5. Synopsys has collaborated with Arm to deliver the next-gen ACE5 and AXI5 VIP with increased performance for faster verification closure.
"AMBA ACE and AXI are used pervasively across a wide range of SoC designs," said Jeff Defilippi, Senior Product Manager, Infrastructure Line of Business, Arm. "ACE5 and AXI5 provide significant performance improvements over previous-generation interconnect protocols, and through collaboration with Synopsys and other partners, we've made it even easier for customers to adopt the latest specifications and achieve multifold productivity gains."
AXI5 and ACE5 added new features for atomic operations to improve the performance and data check and poisoning to identify data corruption. ACE 5 and AXI5 also adds new low power wake-up signals to provide a single, glitch-free indication that activity on the interface is required.
In addition, ACE5 has added support for cache stashing to improve data locality, new de-allocating and cache maintenance transactions, as well as DVM message support for Armv7, Armv8, and Armv8.1 Cortex-A processors.
Synopsys VIP provides performance metrics for latency and throughput analysis, configurable interconnect model, a reference verification platform and system level checks for protocol, data integrity, and cache coherency. Built-in coverage and verification plans are also included to speed up verification coverage closure. In addition, VIP is natively integrated with the Synopsys Verdi Protocol Analyser debug solution.
"We have a strong relationship with Arm and proactively contribute to the development of next-gen interconnect specifications," said Vikas Gautam, Group Director of VIP R&D for the Synopsys Verification Group. "Our partnership enables designers to adopt our ACE5 and AXI5 VIP and test suites and achieve immediate productivity gains."