UltraSoC for RISC-V development with trace and debug

30th April 2018
Posted By : Lanna Cooper
UltraSoC for RISC-V development with trace and debug

UltraSoC has announced that Andes Technology has adopted UltraSoC’s advanced embedded analytics technology for use in its AndesCore range of RISC-V processors. Andes will leverage UltraSoC’s Intellectual Property (IP) offering, including the commercial RISC-V processor trace solution, to accelerate development and enhance debugging of embedded products for sophisticated applications including AI, computer vision, network controllers, and storage.

The two companies will collaborate to demonstrate a complete RISC-V development, debug, and trace flow at the upcoming RISC-V Workshop (7th-10th May, Universitat Poletècnica de Catalunya, Spain).

UltraSoC is offering a commercial RISC-V development environment, with SoC analytics, processor trace and other options available to meet the needs of end customers. A pioneer in the industry, UltraSoC developed processor trace for RISC-V in 2017, and shortly afterwards offered its trace specification for use by the RISC-V Foundation as part of its standardisation effort.

The company remains fully committed to supporting the RISC-V Foundation standard run-control/debug and the proposed processor trace format, in line with its wider strategy of providing integrated debug and development solutions for any processor architecture.

Andes’ cores are based on the high performance AndeStar V5 32-bit and 64-bit architectures. The partnership with UltraSoC allows customers for Andes V5 N25 and NX25 processors to have advanced embedded analytics capabilities integrated as an option. Customers using Andes’ high performance 32 and 64-bit processor cores gain access to UltraSoC’s SoC analytics and debug IP in addition to RISC-V processor trace, which together give designers full visibility not only of the performance of the core but into the operation of the entire system.

Andes has adopted RISC-V for its fifth generation processor architecture, the AndeStar V5, and launched two high-end processor cores in its AndesCore family of configurable processor IP: the 32-bit N25 and the 64-bit NX25. Both are RISC-V based and deliver in excess of 3.4 CoreMark/MHz, with gate counts as small as 30K (N25) and 50K (NX25), and a maximum clock rate of 1.1GHz when using TSMC’s 28nm HPC process. The N25 and NX25 are both suitable for high speed control tasks, and customers choosing either core will benefit from access to UltraSoC’s embedded intelligence.

Charlie Su, CTO and Senior VP of Andes, commented: “The N25 and NX25 AndesCore processors are selected by our customers for their exceptional performance/power, flexible configurations, and comprehensive development tools. Choosing UltraSoC as our preferred partner for embedded analytics, trace and validation gives our customers an advanced development environment with insight into SoC operations and processor execution without disturbing target behaviour.

"UltraSoC has shown itself to be committed to the development of the RISC-V ecosystem and hence it is clearly the best partner for our V5 RISC-V architecture. We are delighted to already be engaged with multiple mutual customers using Andes processor N25/NX25 with UltraSoC’s IP and trace solution to address their demanding applications.”

Rupert Baines, CEO of UltraSoC commented: “We are delighted to be working with Andes on its innovative processor cores for RISC-V, and collaborating with mutual customers on implementations which utilise the power of its leading V5 AndeStar architecture and enable designers full access to the system with the support of UltraSoC’s SoC analytics and debug IP, and processor trace."

RISC-V is an open source instruction set architecture, initially developed by UC Berkeley now being rapidly more widely adopted. UltraSoC and Andes are active members of the RISC-V Foundation, and play active roles in its development. Both companies also participate in all RISC-V Workshops, and will be involved in the upcoming 8th RISC-V workshop in Barcelona.


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