Design
Tundra Semiconductor Announces RapidIO Gen2 Program
Tundra Semiconductor today announced its new RapidIO Gen2 program. Backwards compatible with RapidIO Specification Rev 1.3, Tundra's new RapidIO solutions will offer OEMs increased system performance, reduced power consumption and lower system costs when designing next generation systems.
TundRapidIO 2.0 addresses designers' increased bandwidth requirements by doubling the speed of RapidIO Rev 1.3, increasing link speeds to 6.25 Gbaud and by offering more port choices, increasing flexibility and system level features. New products and IP will enable the deployment of next generation systems with higher processor speeds and aggregation of a larger number of processors while keeping up with real time performance needs. Tundra's commitment to deliver RapidIO Gen2 solutions to the market further strengthens the RapidIO ecosystem, said Tom Cox, Executive Director, RapidIO Trade Association.
Tundra continues to demonstrate its leadership in RapidIO with our RapidIO Gen2 program. RapidIO Gen2 will enable pervasive wireless broadband 4G coverage around the world. Tundra's RapidIO Gen2 IP for DSPs, FPGAs, Microprocessors and ASICs combined with new Gen2 switches will deliver an enhanced end user broadband experience, said Daniel Hoste , President and Chief Executive Officer, Tundra Semiconductor. As a founding member of the RapidIO Trade Association, and Chair of the Technical Working Group, Tundra was a key driver in the development of the RapidIO Gen2 Specification.
With next generation DSPs and microprocessors increasing their performance capabilities and demanding speed requirements up to 6.25 Gbaud, interconnect requirements must increase to fully maximize performance of the processors. RapidIO Gen2 offers link rates from 1.25 Gbaud to 6.25 Gbaud, doubling the speed of RapidIO Rev 1.3, and port widths from x1 to x16 allowing designers to select the port data rate best suited for their application. RapidIO Gen2 continues to allow control plane and data plane traffic to be carried over one interconnect, which results in denser designs, lower overall system power consumption and lower system costs.