TRACE32 Supports MIPS interAptiv Multiprocessor Core Family

TRACE32 supports cross-trigger implementation to handle the debug synchronization among all the cores within the interAptiv processor. Besides on-chip trace, Lauterbach supports also off-chip trace with AUTOFOCUS II MIPI Trace for program-flow and data trace. In addition, TRACE32 offers full OS-awareness for all popular operation systems running on asymmetric multiprocessing, symmetric multiprocessing and mixed systems. To display the registers on a bit field level, TRACE32 provides a peripheral register file for the interAptiv processor.



For many years, Lauterbach has supported the popular MIPS architectures and cores. With TRACE32, the many developers who are creating products around MIPS have access to a full range of debug functionality, from bootstrap code to interrupt routines and drivers, said Norbert Weiss, International Sales and Marketing Manager at Lauterbach.



We are delighted that Lauterbach continue to bring TRACE32 support to new generations of MIPS processors. This includes our widely used MIPS cores featuring hardware multi-threading, which delivers unique benefits for a wide range of applications. Along with software, development tool support is increasingly a key factor in choosing a processor, and Lauterbach is an important partner in our tools ecosystem for MIPS, said Tony King-Smith, EVP Marketing, Imagination.



With its TRACE32 debugger products, Lauterbach provides development tool support for a range of MIPS processors.



MIPS interAptiv Multiprocessor Core Family

Imagination′s interAptiv core is part of the MIPS Aptiv generation of processor IP cores, delivering high-performance multi-threaded, multi-core capabilities. The use of MT, improvements to multi-core performance and additional core enhancements for error correction and power management make interAptiv among the most performance-efficient and feature-rich processor cores in its class.