Technology drives early adoption of next-gen PCIe applications

Posted By : Lanna Cooper
Technology drives early adoption of next-gen PCIe applications


The availability of what the company claims to be the industry’s first Verification IP (VIP) in support of the new PCI Express (PCIe) 5.0 architecture has been announced by Cadence Design Systems.

The Cadence VIP incorporates TripleCheck technology, which lets designers quickly and thoroughly complete functional verification of server and storage System-on-Chip (SoC) designs based on the PCIe 5.0 specification, providing designers with added confidence that designs can function as originally intended.

The differentiated, proven Cadence VIP has supported all recent PCIe standards and has been further optimised for the new 5.0 specification.

Adopters of the PCIe 5.0 specification have access to the Cadence TripleCheck technology, which provides a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with thousands of ready-to-run tests to ensure compliance with the specification.

This enables designers to save time and deliver higher quality end-products. Additionally, designers have access to the Indago Protocol Debug App, which provides protocol-specific interactions between the design, the VIP and the testbench to find the root cause of any design bugs.

“Our team has successfully utilised the Cadence VIP for previous versions of the PCIe specification, which enabled us to deliver world-leading interconnect solutions for compute and storage infrastructures,” said Shlomit Weiss, Senior Vice President, Silicon Engineering at Mellanox Technologies.

“The Cadence solution for PCIe 5.0 is important to our development of the next-gen of our products, to support the need for faster data speeds for high performance, machine learning, cloud, storage and more applications.”

“By offering the first-to-market VIP for PCIe 5.0, enhanced with TripleCheck technology, we’re enabling early adopters to ensure designs are compliant with the specification while achieving the fastest path to IP verification closure,” said Michal Siwinski, Vice President of Product Management and Operations, System and Verification Group at Cadence.

“Our support for the latest protocol demonstrates our commitment to the evolution of the PCIe specification, and customers can start using our solution for PCIe 5.0 immediately.”

The Cadence VIP with TripleCheck technology is part of the Cadence Verification Suite and is optimised for Xcelium Parallel Logic Simulation, along with supported third-party simulators.

The PCIe 5.0 VIP supports the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

The Verification Suite is comprised of core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.


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