This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronised together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM.
The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analysed, showing synchronisation within 50ps without characterised cables or calibrated propagation delays.
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