Cadence Design Systems has announced the Cadence Litho Physical Analyser (LPA) Production Lithography Unified Solution (PLUS) developed in partnership with ASML, which seamlessly provides foundry-enabled lithography simulation capabilities during chip design implementation and signoff. Cadence LPA PLUS enables engineers to detect lithography hotspots during design implementation and physical signoff and automatically fix them in Cadence design platforms.
As a result, designers can improve design reliability and yield, while also accelerating time to market and yield ramp-up of their products.
Cadence LPA PLUS enables engineers to predict and optimise the manufacturability and printability of their designs using a production simulation model and Optical Proximity Correction (OPC) technique from ASML prior to tapeout. This ensures the efficient delivery of high-quality designs that function as intended. In addition, this technology is integrated with the Cadence Virtuoso environment and Innovus Implementation System, providing a simple way to detect and fix printability hotspots during implementation, thereby further optimising design manufacturability and yield.
Cadence and ASML developed the LPA PLUS to address the most complex Design For Manufacturing (DFM) requirements for advanced nodes that industry ecosystem partners demand. Furthermore, the Cadence LPA PLUS solution, validated by imec for advanced node designs, is readily accessible from the designer’s desktop, giving the designer greater control over manufacturability optimisation while reducing foundry iterations.
“At advanced nodes, bridging the gap between design and manufacturing is imperative,” said Christophe Fouquet, Executive Vice President of applications at ASML. “We recognised that the Cadence design solution provided the optimal platform to bring manufacturing awareness to designers. The powerful combination of ASML Brion computational lithography technology and Cadence LPA brings together best-in-class technologies that fill that gap.”
“With Cadence LPA PLUS, engineering teams can simulate the manufacturability of their design at any time during implementation and signoff so they can accelerate time to market,” said Dr. Anirudh Devgan, Senior Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “By working closely with ASML and imec, we’re enabling customers to take control of their design intent, reliability and yield.”
Jason Cain, Principal Member of the technical staff at AMD, said: “As a fabless design company, our designers need access to designer-friendly, production-accurate manufacturability checks. Without this capability, our designers would need to rely on checks run by the foundry, creating lengthy iterations leading to schedule delays. Since Cadence LPA PLUS has been validated by imec, we have increased confidence that our designers can successfully run checks during implementation, optimise the design for yield and stay on schedule with our latest innovations.”