SoC monitoring supports intelligent heterogeneous IP designs

5th June 2019
Posted By : Alex Lynn
SoC monitoring supports intelligent heterogeneous IP designs

It has been announced by UltraSoC that Wave Computing has chosen the company’s embedded analytics and heterogeneous debug technology to test its new TritonAI 64 scalable IP platform for intelligent SoCs (systems on chip). Wave Computing’s use of UltraSoC’s platform will also serve as a reference design for customers needing to validate and debug heterogeneous IP designs.

Wave Computing is partnering with UltraSoC to create a reference architecture for testing, validating and reporting on the performance of SoCs based on the TritonAI 64 Platform. The platform contains three different types of processing engines—WaveFlow, WaveTensor and WaveRT – all based on a single core, the MIPS 32 CPU.

UltraSoC’s analytics and debug platform is perfectly suited to validate this type of system, given its ability to monitor individual processors and report on potential performance or feature issues that may be present in the wider SoC.

UltraSoC offers a complete integrated development environment that combines comprehensive debug, run control, and performance tuning for SoC designers. Having the ability to validate designs in this fashion is especially useful for demanding, high-speed security and public safety use cases leveraging AI, machine learning, automotive or enterprise applications, such as sporting stadiums, airports and train stations.

The expense of verifying and validating an SoC is a prime concern for semiconductor companies, particularly when the device is complex. In particular, over the past few years, chip designers have transitioned from multicore to many-core products, and even heterogeneous multicore SoCs, which integrate many different core processors.

Designing complex SoCs by mixing and matching different semiconductor IP cores is hard enough, but testing and validating those designs can be even more difficult. Most semiconductor companies face challenges surrounding the expense and time it takes to validate these increasingly complex modern designs.

Steve Brightfield, Senior Director of Strategic Marketing for AI and CPU IP licensing at Wave Computing, said: “Given the scalable nature of our new TritonAI 64 platform, it’s essential customers can confidently test the multi-threaded, heterogeneous processor execution of the TritonAI 64 platform for correct operation within their wider system.

“This is especially important in SoC products that employ additional processor architectures or custom logic. UltraSoC’s embedded analytics technology provides a unified view of where in the chip updates need to be made in order to debug and optimise the system. We are positive UltraSoC’s embedded analytics technology will help our customers get even more out of the TritonAI platform for use in any application.”

Embedded SoC technologies present a challenge because of their complex designs and because it is often impossible to view or easily access many of the system components. UltraSoC is committed to overcoming the challenges of SoC designs with embedded monitoring, analytics and debug technology that provides insights into the system-level operation of any SoC.

This ‘embedded intelligence’ enables developers to tackle issues related to complex and heterogeneous designs, where different CPU architectures are used within a single system. UltraSoC’s technology helps significantly ease system bring-up and debug functions, allowing customers to cut time-to-debug by up to 25%.

Rupert Baines, CEO at UltraSoC, added: “We are excited Wave Computing selected our technology for use in its new TritonAI 64 platform, which has enormous potential for bringing AI to thousands of edge applications. 

“As more intelligent technologies come to market with open CPU architectures, often combined with heterogeneous accelerators and other cores, it is important for developers to be able to see how all design elements interact. UltraSoC’s embedded analytics technology is designed from the ground up to be suitable for monitoring and reporting on both heterogeneous and homogeneous CPU architectures.”


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