Design
Ref. design for DSOs, RADAR, and 5G wireless test systems
This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and deterministic latency.
This reference design demonstrates multi-channel AFE and clock solution using high speed data converters with JESD204B, high speed amplifiers, high performance clocks and low noise power solutions to achieve optimum system performance
Features
- 3.2Gsps, 1.5GHz multi- channel high speed analog front for high performance receiver
- < 5ps clock skew between channels
- Multi-channel JESD204B complaint clock solution
- Scalable platform for pin compatible ADC12DJxx00 family
- Supports TI’s high-speed converter and capture cards (TSW14J56 / TSW14J57)
Discover more here.
Product Spotlight
APV1111GVY
Panasonic
Panasonic PhotoMOS® Photovoltaic MOSFET High-Power Drivers
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| Stock: | 3490 |
| Cost: | $3.95 |
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