Physical implementation solution provides 10-20% better PPA

11th March 2015
Posted By : Siobhan O'Gorman
Physical implementation solution provides 10-20% better PPA

A physical implementation solution, which enables SoC developers to deliver designs with outstanding PPA (Power, Performance and Area), has been introduced by Cadence Design Systems. Driven by a massively parallel architecture with breakthrough optimisation technologies, the Innovus Implementation System provides typically 10-20% better PPA and five to ten times full-flow speedup and capacity gain at advanced 16/14/10nm FinFET processes and established process nodes.

The system was designed with several key capabilities to help physical design engineers achieve outstanding performance while designing for a set power/area budget or realise maximum power/area savings while optimising for a set target frequency. The key Innovus capabilities to achieve this include:

  •  New GigaPlace solver-based placement technology that is slack driven and topology-/pin access/coloraware, enabling optimal pipeline placement, wire length, utilisation and PPA, and providing the best starting point for optimisation.
  •  Advanced timing- and power-driven optimisation that is multi-threaded and layer aware, reducing dynamic and leakage power with optimal performance.
  • Unique concurrent clock and datapath optimisation that includes automated hybrid H-tree generation, enhancing cross-corner variability and driving maximum performance with reduced power.
  • Next-generation slack-driven routing with track-aware timing optimisation that tackles signal integrity early on and improves post-route correlation.
  • Full-flow multi-objective technology enables concurrent electrical and physical optimisation to avoid local optima, resulting in the most globally optimal PPA.

The Innovus Implementation System also offers multiple capabilities that boost turnaround time for each place and route iteration. The system’s core algorithms have been enhanced with multi-threading throughout the full flow, providing significant speedup on industry-standard hardware with 8 to 16 CPUs. Additionally, the Innovus Implementation System features the industry’s first massively distributed parallel solution that enables the implementation of design blocks with 10 million instances or larger. Multi-scenario acceleration throughout the flow speeds runtime even with an increasing number of multi-mode, multi-corner scenarios.

In addition to providing outstanding PPA and optimised turnaround time, the system offers a common UI across synthesis, implementation and signoff tools, and data-model and API integration with the Tempus Timing Signoff solution and Quantus QRC Extraction solution. Together these solutions enable fast, accurate, 10nm-ready signoff closure that facilitates ease of adoption and an end-to-end customisable flow. Customers can also benefit from robust visualisation and reporting that enables enhanced debugging, root-cause analysis and metrics-driven design flow management.

“Customers have already started to employ the Innovus Implementation System to help achieve higher performance, lower power and minimised area to deliver designs to the market before the competition can,” said Anirudh Devgan, Senior Vice President, Digital and Signoff Group, Cadence. “The early customers who have deployed the solution on production designs are reporting significantly better PPA and a substantial speed up in turnaround time reduction versus competing solutions.”

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