A massively parallel, cloud-ready physical verification signoff solution has been announced by Cadence Design Systems. The Pegasus Verification System enables engineers to deliver advanced-node ICs to market faster. The new solution is part of the full-flow Cadence digital design and signoff suite and provides up to ten times faster Design Rule Check (DRC) performance on hundreds of CPUs while also reducing turnaround time from days to hours versus the previous generation Cadence solution.
Early adopters are already using the Pegasus Verification System for large-scale designs, across storage, high-performance computing, cloud, server and mobile applications. The solution offers customers the following benefits:
Texas Instruments (TI), an early Cadence Pegasus Verification System customer, was able to successfully scale the new solution with significant improvements. The Pegasus Verification System’s native cloud processing capabilities delivered improved turnaround times when compared with TI’s incumbent solution.
Additionally, Scott Barrick, Senior Manager of advanced engineering services at Microsemi, said: “As technology nodes advance, Microsemi is leveraging the Cadence Pegasus Verification System to shorten our time to tapeout. Its near-linear scalability can enable us to scale full-chip DRC runs to hundreds of CPUs for short periods and achieve up to ten times the speedup when compared with the previous-generation Cadence solution. The next-gen solution offers native cloud support and gigascale processing, giving us the flexibility to add hundreds of CPUs for peak usage during tapeout while achieving our desired runtime.”
“Engineers have experienced increasing DRC complexity at advanced nodes, and current DRC solutions can’t support the turnaround requirements needed to ensure that design schedules are met,” said Dr. Anirudh Devgan, Executive Vice President and General Manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “The Pegasus Verification System’s innovative architecture and native cloud-ready processing provides an elastic and flexible computing environment, which can enable our customers to complete full-chip signoff DRC on advanced-node designs in a matter of hours, speeding time to market.”
The new Pegasus Verification System continues to extend the organic innovation within the Cadence digital design and signoff suite. The suite includes a comprehensive full flow from synthesis through implementation and signoff, offering what it claims to be the fastest path to achieve Power, Performance and Area (PPA) targets across a wide variety of applications and vertical segments. The addition of the Pegasus Verification System to the full-flow suite also supports the company’s broader System Design Enablement (SDE) strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.