Low cost tester for flexible Boundary Scan applications

2nd October 2007
Posted By : ES Admin
Low cost tester for flexible Boundary Scan applications
GÖPEL electronic has introduced the ScanBooster Designer Studio, a new family of low cost test systems. Based on a powerful JTAG/Boundary Scan Controller with Plug and Play USB2.0 interface, combined with a special edition of the integrated development environment CASCON GALAXY, this new offering is especially suited for the rapid verification of prototypes.
“With this new product family we offer for the first time a complete, pre-configured solution for specific target applications, further widening our already extensive product portfolio”, says Karl Miles, Sales Manager at GOEPEL electronics UK. “The modularity of our hardware and software offers a unique flexibility, allowing our users to extend their Boundary Scan systems as their requirements grow. As a result, we offer powerful systems at a minimal initial cost, while the customer's investments are protected even if new capabilities are required at some point in the future”.



ScanBooster Designer Studio supports one Test Access Port (TAP), which can be upgraded in terms of hardware and software to support up to eight independent and parallel TAPs.

The ScanBooster Boundary Scan Controller is powered through the USB bus (eliminating the need for a separate power supply) and provides a number of additional resources, such as 32 Bit parallel I/O, 2 analogue channels with A/D and D/A conversion, trigger signals, as well as voltage, impedance and up to 16MHz TCK programmability of the TAP interface(s), supporting a wide variety of test strategies and even mixed signal applications.



The ScanBooster Designer Studio Boundary Scan Software includes the complete CASCON GALAXY device library, BSDL import and export tools, as well as import processors for more than 80 CAD data formats. Applications for the software range from testability analysis of new UUT designs to automated verification of device pin connectivity on high density devices such as Ball Grid Arrays (BGA). Open pins or shorted nets (bridging faults) are reliably detected. Algorithmic test procedures for any kind of cluster tests can easily and efficiently be created manually in the integrated mixed-signal programming language CASLAN.

In addition, the system includes a comprehensive and powerful Multi-Mode Debugger for in-system verification of the JTAG/Boundary Scan circuitry as well as non-Boundary Scan circuit functions. The debugging tools can visualize all JTAG accessible device registers, TAP Controller states, as well as logic states on nets and individual pins, providing valuable insight into the Unit Under Test circuitry and supporting the user during fault analysis and prototype validation/verification, for instance.



All test programs are cross-compatible with all Boundary Scan Controllers by GÖPEL electronic, including the award-winning hardware platform SCANFLEX®. The wide variety of software options that can be added on to the tool set include graphical Visualizers for layout and schematic, Automated Test Program Generation (ATPG) tools for the automated test of non-Boundary Scan circuitry, an interactive Pin Toggler Tool, as well as options for automated in-system programming for FLASH and Serial EEPROM.




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