Lattice Announces 4 x 3.125Gbps SRIO Capability On The Mid-Range LatticeECP3 FPGA family

This is an extension of the previously announced SRIO v2.1 core that originally supported 1x and 2x up to 3.125Gbps and 4x up to 2.5Gbps. This core can be demonstrated utilizing the industry standard Lattice Advanced Mezzanine Card (AMC) form factor platform. With this announcement, Lattice demonstrates its continued leadership in mid-range FPGAs, supporting all lane configurations/rates of high speed serial protocols such as Level 1 SRIO.

“By offering an industry leading 1x, 2x and 4x up to 3.125Gbps SRIO solution on a low power, mid-range platform, our LatticeECP3 family achieves higher performance levels that have been traditionally addressed only by high end FPGAs,” said Ron Warner, Vertical Marketing Manager, Wireless Infrastructure.


About the Serial RapidIO 2.1 IP Core

• Allows for 1x, 2x and 4x lane configurations
• Supports up to 3.125Gbps
• Implements physical layer, transport layer, maintenance transaction handling and error management extensions
• Provides infrastructure support for external logical layer functions, enabling maximum flexibility
• Provides a choice of how logic layer functions interact with the rest of the system - SoC bus or streaming interfaces
• Supports software implementations of control plane-oriented functions such as doorbells and messages
• Backward compatible with the v1.3 specification